OC-192系統之互補式金氧半10Gb/s資料時脈回復電路設計與製作

Design and Implementation of CMOS 10Gb/s Clock-and-Data Recovery Circuit for OC-192 System

傅家煌(Chia-Huang Fu)

指導教授 ： 汪重光

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.01073

摘要

隨著對傳輸速率需求的不斷提昇，廣域網路以及骨幹網路的串列資料通訊已經演進到了每秒百億位元的等級。SONET和SDH已發展成為光纖通訊中高傳輸速率的應用。III-V族以及SiGe HBT的製程過去大部分被使用在億位元等級傳送接收機的高速電路中。而當CMOS製程演進到深次微米技術，10Gb/s OC-192和40Gb/s OC-768的傳送接收機也可使用CMOS來實現，並且因為其低成本、低必v、和高度整合的優勢而漸成主流。由於光纖本身的特性，再生器在長距離光纖傳輸當中佔了很重要的位置。在SONET / SDH的網路當中，可能出現上百或上千次的信號再生，因此時域擾動的移轉頻寬和最大值都有嚴格的規格要求，同時也對OC系統中資料時脈回復電路的設計造成很大的挑戰。
本論文介紹了三個OC系統的積體電路晶片。第一個是以0.18µm 1P6M CMOS 製程完成的OC-192半速率壓控震盪器。本晶片以0.66 × 0.95 mm2的面積完成了5GHz的震盪頻率和寬的調整範圍。在1.8伏特的電壓下總消耗必v為6毫瓦。第二個晶片是OC-768系統的半速率壓控震盪器和注射鎖定式除二電路。可接受21.6GHz輸入信號的注射鎖定式除頻器是以0.13µm 1P8M CMOS實現。在1.2伏特的電壓下總消耗必v為4.8毫瓦。最後一個是OC-192系統的資料時脈回復電路。此電路使用了改良式的D型正反器和電感電容式壓控震盪器，以0.18µm 1P6M CMOS製程來達成全速率的資料時脈回復。在1.8伏特的電壓下總消耗必v為91毫瓦，所佔面積為1.18 × 0.85 mm2。所有的晶片都經過佈局後模擬驗證，同時前兩個電路的量測結果也會一併呈現。

關鍵字

壓控震盪器 ； 互補式金氧半 ； 資料時脈回復電路設計

並列摘要

With the growing demand on transmission rate, the serial data communication has evolved into tens of gigabits per second for wide area network (WAN) and the backbones. Synchronous Optical NETwork (SONET) and Synchronous Digital Hierarchy (SDH) have been developed to work at high transmission rates over optical fiber. High-speed circuits in multi-gigabits per second transceivers were mostly implemented in III-V technology or SiGe HBT. While CMOS process migrates into deep submicron technology, transceiver circuits of 10Gb/s OC-192 and 40Gb/s OC-768 on CMOS are achievable and becoming the mainstream for low cost, low power and high integration. Because of the characteristic of fiber, regenerators are essential for long-distance optical transmission. Hundreds to thousands of regeneration is possible within a SONET / SDH network, so stringent jitter transfer bandwidth and jitter peaking specifications pose great challenges on the design of a clock-and-data recovery (CDR) circuit for Optical Carrier (OC) system.
This thesis presents three chips for OC system. The first one is a half-rate voltage-controlled oscillator (VCO) for OC-192 system in 0.18µm 1P6M CMOS technology. Occupying an area of 0.66 × 0.95 mm2, 5GHz oscillation frequency with wide tuning range is achieved. It consumes a power of 6mW under 1.8V supply. The second chip is a half-rate VCO along with an injection-locked divide-by-two circuit for OC-768 system. Fabricated in 0.13µm 1P8M CMOS technology, an injection-locked frequency divider (ILFD) for 21.6GHz input is realized. The power consumption of ILFD is 4.8mW under 1.2V supply voltage. The final one is a CDR for OC-192 system. By applying a modified D flip-flop (DFF) and LC-tank VCO, a full-rate CDR is achieved in 0.18µm 1P6M CMOS technology. The chip occupies an area of 1.18 × 0.85 mm2 and consumes a power of 91mW under 1.8V supply. All the chips are verified from post-layout simulation and the former two are presented with measurement results.

並列關鍵字

VCO ； CMOS ； OC-192 ； OC-768 ； clock-and-data recovery ； CDR ； 10Gb/s ； bang-bang PD ； wide-tuning range

參考文獻

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[4] A. Hajimiri, and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE J. Solid-State Circuits, Feb. 1998.

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