多工環境下之快取記憶體漏電流管理

由於手持設備的普及，在嵌入式系統上，能量消耗成為一個主要的議題。除了動態能量(dynamic energy)之外，靜態能量(static energy)也就是系統漏電近年來也越來越受到重視。有預估報告指出，當製程技術進步到.07時，系統漏電將會佔據全部能源的百分之七十，所以近年來，就有兩種的電路被設計來降低快取記憶體裡的漏電流，也就是State-destructive 和State-preserving，這些電路提供了記憶體低漏電模式，而當有了電路的供給後，也就有一些控制的方法被提出來控制何時需把記憶體放入低漏電模式。過去的快取記憶體漏電流管理研究都專注在單一一個應用程式的特性，不過在實際的系統上，快取記憶體是被多數個程序所共享，因此在這篇論文，我就會利用程序的資訊去管理快取記憶體漏電流。我會根據每一個程序的工作量去分配給其適合的快取記憶體大小，然後分別給執行及暫停的程序不一樣的漏電流管理方法，用這樣的方法，可以省掉第一階層快取記憶體百分之八十四的漏電流，而且不會造成任何的效能損失。

關鍵字

快取記憶體；漏電流；多工環境

並列摘要

Power consumption is becoming a critical design issue of embedded systems due to the popularity of portable device such as cellular phones and personal digital assistants. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Leakage is projected to account for 70% of the cache power budget in 70nm technology. In recent year, two kinds of circuit technique are presented for reducing leakage consumption in cache cells: state-destructive and state-preserving. Most leakage energy can be reduced by using effective control to switch leakage mode. Previous works on cache leakage management are all based on single-application behavior. In real workloads, caches are actually shared by multiple processes. In this paper, I utilize the task-level information to manage cache leakage power. I partition the caches among tasks according to their working set size. I then apply different leakage management policies to the cache regions allocated to active and suspended tasks, respectively. My proposed policies effectively reduce L1 cache leakage energy by 84% on the average for the multi-programming workloads with only negligible degradations in performances.

並列關鍵字

Cache ； Leakage ； Multiprogrmming

參考文獻

[1] N. Majikian and T. S. Abdelrahman, “Drowsy instruction caches:leakage power reduction using dynamic voltage scaling and cache sub-bank prediction,” in Proc. 35th Ann.

[2] S. Kaxiras, Z. Hu, and M. Martonosi, “Cache decay: Exploiting generational behavior to reduce cache leakage power,” in Proceedings of the 28th Annual International

[3] K. Flautner, N.S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy caches: Simple techniques for reducing leakage power,” in International Symposium on Computer

[6] D. Brooks, V. Tiwari, and M. Martonosi., “Wattch: A framework for architectural-level power analysis and optimizations,” in In Proceedings of the 27th International

Symposium on Computer Architecture (ISCA), 2000.

國際替代計量

多工環境下之快取記憶體漏電流管理

全文下載

主題瀏覽