一個應用於HEVC中的進行反量化及反離散餘弦變換之高效率管線化超大型積體電路架構

An Efficient Pipelined VLSI Architecture for Inverse Quantization and Discrete Cosine Transform in H.265/HEVC

陳乃鈞(Chen, Nai Chun)

指導教授 ： 林永隆

國立清華大學/電機資訊學院/資訊工程學系/碩士(2015年)

摘要

在本論文中，我們提出一個應用於HEVC main profile的包含系數掃描、反量化以及反離散餘弦變換之硬體架構。本設計支援4x4，8x8以及16x16大小的轉換方塊。架構中包含了一個掃描單元、一個用於反量化的雙階層管線化單元、一個可重複利用的反離散餘弦變換單元，以及相對應的控制單元。本設計可支援3840x2160解析度的60FPS影片。

關鍵字

HEVC ； 硬體 ； 管線化

並列摘要

We propose a hardware implementation including coefficient scanning, inverse quantization and inverse discrete cosine transform for HEVC main profile in this thesis. The design supports 4x4, 8x8 and 16x16 sized transform blocks. It includes a scanning unit, a two-stage pipelined architecture for inverse quantization, a reusable architecture for inverse discrete cosine transform and corresponding control units. The proposed design can support real time decoding of 3840 x 2160 video at 60 fps.

並列關鍵字

HEVC ； Hardware ； Pipelined

參考文獻

[11] W.-H. Chen, C. H. Smith, and S. C. Fralick "A fast computational algorithm for the discrete cosine transform," IEEE Transactions on Communications, vol.25, No.9, pp.1004-1009 Sep. 1977.

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[4] P.Kumar, Sang-Yoon Park, B.Kumar, Khoon-seong Lim, and Chuohao Yeo, "Efficient Integer DCT Architectures for HEVC," IEEE Transactions on Circuits and Systems for Video Technology, volume24, issue 1, pp. 168-178, 2014.