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Method of making high voltage linear P-buried rings ldmos with improved rdson

Method of making high voltage linear P-buried rings ldmos with improved rdson

指導教授 : 許健
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摘要


Dr. Gene Sheu, Nithin,D P. 2010. Method of making High-Voltage Linear P-Buried Rings LDMOS Transistors with improved RDSon. Analog-BCD Laboratory, Asia University, Taiwan For UHV power IC applications, Device must deliver a very high breakdown voltage, low on-state resistance with reasonable SOA performance. The current device structures such as Double RESURF P-top, Buried P-top or vertical linear doping with JI technology will meet the desired specifications, but fail to meet the desired specifications when tested with cylindrical or racetrack layout due to current crowding effect. Surface doping profile indicates a huge drop in doping concentration near the source region compared with drain region, causes pinch-off effect which leads to higher On-state resistance. Based on the analytical model developed by Dr. Gene Sheu et al., for Double resurf Buried P-top LDMOS has a very good agreement with simulation results, further enhancing the structure with P-Buried linear rings with enhanced N-top surface implant results in dual conduction path for the structure. Using different size buried linear P-top rings and varying the spacing between them, we are able to manipulate the electrical field at both ends which is critical to meet desired results with circular shape (Racetrack) design to reduce the field, LDMOS with dual conduction path seems to offer the solution which is less expensive and less complicated than Super-Junction device. Source centric mask design proposed by S H Lee et al., of Fairchild Semiconductors has a BVoff of 750V along with 150m.ohm.cm2 RDSon. In this proposed structure defining P-buried linear rings with single mask (No additional mask is required for the current process) by just changing the layout mask (varying the total N-dose for cylindrical structure and tested in cylindrical structure) can make the device deliver required breakdown voltage for all regions. By introducing enhanced N-top conduction layer it is able to increase the doping concentration substantially near the source which eliminates the pinch-off effect and reduces on-state resistance of 108m.ohm.cm2 while maintaining BVoff of above 800V.

關鍵字

低電阻 電壓 半導體

並列摘要


Dr. Gene Sheu, Nithin,D P. 2010. Method of making High-Voltage Linear P-Buried Rings LDMOS Transistors with improved RDSon. Analog-BCD Laboratory, Asia University, Taiwan For UHV power IC applications, Device must deliver a very high breakdown voltage, low on-state resistance with reasonable SOA performance. The current device structures such as Double RESURF P-top, Buried P-top or vertical linear doping with JI technology will meet the desired specifications, but fail to meet the desired specifications when tested with cylindrical or racetrack layout due to current crowding effect. Surface doping profile indicates a huge drop in doping concentration near the source region compared with drain region, causes pinch-off effect which leads to higher On-state resistance. Based on the analytical model developed by Dr. Gene Sheu et al., for Double resurf Buried P-top LDMOS has a very good agreement with simulation results, further enhancing the structure with P-Buried linear rings with enhanced N-top surface implant results in dual conduction path for the structure. Using different size buried linear P-top rings and varying the spacing between them, we are able to manipulate the electrical field at both ends which is critical to meet desired results with circular shape (Racetrack) design to reduce the field, LDMOS with dual conduction path seems to offer the solution which is less expensive and less complicated than Super-Junction device. Source centric mask design proposed by S H Lee et al., of Fairchild Semiconductors has a BVoff of 750V along with 150m.ohm.cm2 RDSon. In this proposed structure defining P-buried linear rings with single mask (No additional mask is required for the current process) by just changing the layout mask (varying the total N-dose for cylindrical structure and tested in cylindrical structure) can make the device deliver required breakdown voltage for all regions. By introducing enhanced N-top conduction layer it is able to increase the doping concentration substantially near the source which eliminates the pinch-off effect and reduces on-state resistance of 108m.ohm.cm2 while maintaining BVoff of above 800V.

並列關鍵字

Rdson BVoff SOA Buried-P

參考文獻


[1] An Analytical Model of Surface Electric Field Distributions in Ultra High-Voltage (800 V) Buried P-top Lateral Diffused Metal-Oxide-Semiconductor Devices JJAP-2009 by Gene Sheu, Shao-Ming Yang*, Yi-Fong Chang, and Shyh Chang Tsaur
[3] H. Vaes and J.Appels,“High voltage, high current lateral devices,” IEDM Tech.Dig, 1980, pp.87-90.
[4] E. Wildi, P. Gray, T. Chow, H. Chang and M. Cornell, “Modeling and process implantation of implanted RESURF type devices,’ IEDM Tech.Dig, 1982, pp.268.
[5] A. Ludikhuize, “ A review of RESURF technology,” Proc. of ISPSD, 2000, pp.11-18.
[9] Prof. Dr. Helmut Föll, Semiconductors online edition www.tf.uni-kiel.de/matwis