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  • 學位論文

以DCT為基礎之靜態影像壓縮與TI DaVinci上的實現之研究

The Study of A DCT-based Still Image Compression and Implementation on TI DaVinci

指導教授 : 陳彥霖
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摘要


在本論文中,為了能夠在嵌入式板子上執行我們所提出的靜態影像壓縮演算法,我們使用低複雜度的與低記憶體資源使用量的各種編碼方式,來達到快速、高畫質(PSNR值)和高壓縮倍率的靜態影像壓縮技術。因此,我們發展一套以離散餘弦轉換 (Discrete Cosine Transform,DCT)為基礎來做各種改良。我們以更快速、結構更簡單的FCT(Fast Cosine Transform)取代DCT轉換,另外,我們加入視覺感知編碼 (Perceptual Coding for Vision)以提高影像壓縮品質。在量化器上,加入量化階偏移 (Step Size Offset)來增進壓縮量。接著,利用所有DCT區塊中的DC (Direct Current)值之間的關聯性來建立前文模型 (Context Model),並用誤差訊號編碼(Differential Pulse Code Modulation,DPCM),來縮小資料量以增進壓縮率。為了更有效率的進行後續的編碼(Encoding),我們使用ZTC(Zerotree Coding)來掃描所有係數,並使用複雜度較低的GR_FS(Golomb-Rice Fundamental Sequence)來編碼,以提升壓縮率。 接著以德州儀器 (TI) 所開發的DSP DM6446來實現。DM6446 開發板內含TMS320C64x+™ DSP 核心、ARM926 處理器,ARM 負責作業系統應用,DSP負責執行影音編碼器(Codec)演算法處理。本論文透過改寫演算法、善用硬體資源等方式,來增進處理速度,希望能有好的執行效能。

關鍵字

DCT 靜態影像壓縮 視覺認知編碼 ZTC DSP

並列摘要


In this thesis, in order that we can execute our algorithm of still image compression on embedded system, we use the low-complexity and low-memory coding ways to reach a still image compression technique with high speed, high image quality and high compression ratio. So, we develop a way that is based on Discrete Cosine Transform (DCT) and refine it. Instead of DCT transformation, we use Fast Cosine Transform (FCT) that is faster and simpler than DCT. Furthermore, we add a perceptual coding for vision to increase the image compression quality and employing step size offset in quantization for improvement of compression ratio. Next, we establish context model by the relation between DC values of all DCT blocks, and use differential pulse code modulation to reduce quality of data. For more effective encoding, we scan coefficients by zerotree coding, and use Golomb-Rice Fundamental Sequence to improve compression ratio. Next, our codec is implemented on DM6446 which is developed by TI. DM6446B board includes TMS320C64x+™ DSP kernel and ARM926 processer. The purpose of the ARM is the application of operation system, DSP execute the algorithm of video codec. In this thesis, we use some efficient algorithms and make good use of hardware to increase processing efficiency, we expect that he efficacy of DaVinci board can be enhanced by our algorithm. it can get more efficient capability on board.

並列關鍵字

DCT still image compression perceptual coding ZTC DSP

參考文獻


[11] A. C. Cheng, “Development of Computer -vision-based Vehicle Safety Protection Techniques on TI DaVinci Dual-Core Platform,” M.S. thesis, Department of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C., July 2008.
[2] C. M. Hsieh, “The Study of Vision-Based Intelligent Driver Assistance and Real-Time Video Compression System,” M.S. thesis, Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., Sep. 2007.
[3] H. S. Chang, and K. Kang, “A Compressed Domain Scheme for Classifying BlockEdge Patterns,” IEEE Trans. Image Process., vol. 14, no. 2, pp. 145-151, Feb. 2005.
[5] Y. L. Lee, H. C. Kim and H. W. Park, “Block Effect Reduction of JPEG Image by Signal Adaptive Filteing,” IEEE Transactions on Image Processing, vol. 7, no. 2, pp. 229-234, Feb. 1998
[7] H. Li, G. Liu, and Y. Li, “An Effective Approach to Edge Classification From DCT Domain,” IEEE ICIP’02, vol 1, pp. 940-943, Sep. 2002.

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