感知老化效應的路徑延遲分析之實現

Implementation of Aging-Effect-Aware Path Delay Analysis

李宜諺(Yi-Yen Li)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201900582

摘要

電路老化(aging)會影響電路的可靠度，因此如何分析老化效應對電路所帶來的影響是很重要的議題。過去有許多研究透過建立電晶體衰退模型(transistor degradation model)以及邏輯閘延遲衰退模型(gate delay degradation)來估計老化效應對邏輯閘延遲以及路徑延遲(path delay)的影響。
在這篇論文中我們僅分析負偏壓溫度不確定性(Negative-bias temperature instability)對路徑延遲的影響，引用過去研究的電晶體衰退模型，並建立自己的邏輯閘延遲衰退模型，實現了一個能感知老化效應的路徑延遲分析流程。實驗結果顯示以我們的邏輯閘延遲衰退模型估算的邏輯閘輸出訊號傳播延遲(propagation delay)誤差低於2 ps，同時能夠順利地計算出受老化效應影像後的路徑延遲，誤差最大值為8.27%。

關鍵字

電路老化 ； 負偏壓溫度不確定性 ； 電晶體衰退模型 ； 邏輯閘延遲衰退模型 ； 路徑延遲

並列摘要

Aging effect has become one of major causes for reliability degradation of VLSI design. To analysis the circuit performance degradation is a significant issue. Several aging effect researches have been proposed to build transistor degradation model and gate delay degradation model.
In this paper, we proposed a flow to analyze the path delay degradation caused by Negative-Bias Temperature Instability (NBTI). We implement the method by citing a previous work and building our own gate delay degradation model. In the experiment result, we can estimate the gate propagation delay by our model with error within 2 ps. We can successfully calculate the target path delay degradation affected by NBTI, and the errors are below 8.27%.

並列關鍵字

aging ； negative-bias temperature instability ； transistor degradation model ； gate delay degradation model ； path delay

參考文獻

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