現代繪圖晶片之精確週期模擬器

現代繪圖晶片提供比一般中央處理器更多的平行度與運算能力，讓繪圖晶片在目前學術研究慢慢的受到重視。為了提供高平行度的運算，繪圖晶片會分組所有的執行緒並使用單一指令來排程執行一組中的多個執行緒，利用這種大量平行化的執行方式，簡化控制硬體的花費用來提升計算硬體能力。現在的繪圖晶片研究都沒有考量與實做硬體微架構細節，例如可程式化處理器的微架構：指令單元、排程單元、貼圖管線、等等；而實驗部分太注重在通用運算應用，而非最重要的圖學應用，圖學應用乃是繪圖晶片設計最基本的目的。經由收集許多論文、專利、公開資料，本論文是第一個有整理出一套合理之類似NVIDIA 繪圖晶片中可程式化處理器微架構，並針對OpenGL ES 應用程式平台實做出模擬器框架的研究，模擬器框架包含：繪圖晶片模擬器、前端OpenGL ES 平台程式轉換成模擬器的工具鏈（擷取器、編譯器、驅動程式）。我們利用模擬器框架實做出五個具有代表3D 繪圖領域重要的繪圖技術核心應用來實驗探索繪圖晶片之執行模式的設計空間，我們發現一味增加計算能力來提升平行度會使得有較多運算的程式有較多的好處，但是對於跳躍分歧（branch divergence）的影響則相對加劇，使得硬體使用率變差，反而傷害效能，無法使得效能依照運算能力等比的上升。此外對於3D 繪圖程式中貼圖行為的比重與繪圖晶片同時可執行的執行緒組數目會影響有多少的記憶體存取延遲可以被隱藏，因此不同的程式特性會對應到一種適合的計算能力與同時執行緒組數目的比率，來達到同時最大化運算平行度與隱藏延遲的能力。

關鍵字

繪圖晶片架構；單指令多執行緒執行架構；模擬器；貼圖管線；三維圖形測量標準程式

並列摘要

Modern Graphic Processing Units (GPUs) has obtained a lot of attention recently since it provides orders of magnitude more computing power than CPUs. GPUs adopt the SIMT (Single Instruction Multiple Threads) execution model, which groups several threads into a warp for scheduling and execution. Current studies on GPUs are often based on an abstraction level of the SIMT execution model, and focus only on non-graphics applications. Micro-architectural details on fetch logics, warp scheduling units, and texture pipelines are not modeled. This thesis attempts to sketch the complete GPU micro-architecture that supports SIMT execution. Due to the limited information released from major GPU vendors, we derive an Nvidia-like GPU architecture through extensive patent search. A cycle-accurate simulator is also developed. We evaluate SIMT execution efficiency on a set of 3D graphics kernels with complicated shading effects. We explore the design space of the SIMT pipeline width, the number of concurrent warps, and the trade-off between these two factors. We make the following observations. First, wider SIMT pipeline benefits computation -bound workload but its performance is limited by branch divergence. Second, texture performance plays an important role for 3D graphics application. For applications with high texture accesses, the number of concurrent warps is critical to performance.

並列關鍵字

GPU Architecture ； SIMT Execution Model ； Simulator ； Texture Cache ； Graphics Benchmarks

參考文獻

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國際替代計量

現代繪圖晶片之精確週期模擬器

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