PAC雙核心系統晶片設計開發實務與應用

Practices and Application of PAC Duo SoC Design

紀坤明(Kung-Ming Ji) ； 葉人傑(Jen-Chieh Yeh) ； 劉俊男(Chun-Nan Liu) ； 林泰吉(Tay-Jyi Lin)

《電腦與通訊》 132期 (2010/04) Pp. 65-71

https://doi.org/10.29917/CCLTJ.201004.0010

摘要

工研院PAC(Parallel Architecture Core)計畫起始於2003，目標為開發出用於多媒體應用之高效能低功耗可程式硬體平台。於PAC計畫初始階段(2004~2006)時，先開發出有多項專利保護之5-wayVLIW DSP (PACDSP)。近期則以ARM9+2 PACDSP設計出一個異質三核心系統單晶片－PAC Duo，以TSMC 90nm製程下線之後，它可做H.264解碼與object detection等多媒體及影像處理等應用，展現多核心之高效能及針對多媒體應用方面的高能量效率。為協助下一代單晶片–PAC Duo+之架構研討，電子系統層級(ESL)分析技術亦被應用於此計畫；另外，為了可以連接網路服務，Google的Android軟體平台與OpenCORE多媒體library也成功的被實現並驗證於PAC Duo單晶片。

關鍵字

PAC ； Android平台 ； 三核心 ； 電子系統層級 ； 動態電壓與頻率調變 ； 低功率

並列摘要

The PAC (Parallel Architecture Core) project of Industrial Technology Research Institute (ITRI) was initiated in 2003. The objective of this project is to develop a low-power and high-performance programmable platform for multimedia applications. In the first phase (2004~2006), a 5-way VLIW DSP (PACDSP) processor has been developed with our distributed & ping-pong register file and VLIW encoding techniques which are patented. Recently, a tri-core PACDSP-based SoC, PAC Duo (ARM9 + two PACDSP cores), has also been designed and fabricated in TSMC 90nm technology to demonstrate the high performance computing and energy saving efficiency for multimedia and image processing such as H.264 decoding and object detection. To assist with architectural exploration of next-generation PAC Duo SoC (project code: PAC Duo+), the technology of electronic system-level (ESL) analysis together with power information are utilized. In order to to link with Web-based services, the Google Android software stack and OpenCORE-based multimedia library are also implemented and verified on this PAC Duo SoC.

並列關鍵字

Parallel Architecture Core ； PAC ； Android Platform ； Tri-Core ； Electronic System Level ； ESL ； Dynamic Voltage & Frequency Scaling ； DVFS ； Low Power