- 學位論文
適用軟體定義無線電之可調變類比前端電路設計
Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends
摘要
此篇論文設計了一個適用於軟體定義無線電之可數位程式控制的低通濾波器。為了達成高階的濾波器設計，在此我們串接由單級操作放大器所構成的主動式轉導電阻電容之架構。此架構結合了轉導電容濾波器（吳寄生極點）與主動電阻電容濾波器（高線性度）的優點。此外，在我們所需的操作截止頻率中，它提供了可數位程式控制的頻寬與功率消耗。 在此論文中我們討論兩個同一架構，不同製成的晶片。一是實現於0.18um CMOS製成，操作於1.8v的電壓。另一晶片則是實現於90nm CMOS製成，操作於1.2v的電壓。 0.18um CMOS的低通濾波器提供了0.54MHz到15.71MHz 的切換頻率範圍。雜訊的範圍則取決於截止頻率而落在47.9nV/Hz到186nV/Hz之間，功率消耗則是0.69mW 到 21.6mW. 晶片的面積為1.43 * 1.42 mm2. 90nm CMOS的低通濾波器則是提供了0.13MHz到30MHz 的切換頻率範圍。雜訊的範圍為87nV/H，功率消耗則是0.83mW 到 25.73mW. 晶片的面積為1.3 * 1.2 mm2.
並列摘要
This thesis presents an approach to design a digitally programmable low pass filter intended for a software-defined radio (SDR) front-end. To obtain high-order filtering, we exploit a cascade of single-amplifier biquadratic sections, namely active-Gm-RC and Rauch. These cells combine the advantage of Gm-C filters (no parasitic poles) with the advantages of Active-RC filter (large linear range). Furthermore, they provide digitally programmable bandwidth and power consumption with a fully customizable cut-off frequencies range. The realized chips in this work can be generally divided into two categories to their technology. One is realized in 0.18um CMOS technology with 1.8-V supply voltage and the other is realized in 90nm CMOS technology with 1.2-V supply voltage. The 0.18um LPF provides a frequency tuning range between 0.54MHz and 15.71MHz with noise level between 47.9nV/Hz and 186nV/Hz whereby the power consumption conveniently varies from 0.69mW to 21.6mW. The die area is 1.43 * 1.42 mm2. The 90nm LPF provides a frequency tuning range between 0.13MHz and 30MHz with noise level between 87nV/Hz whereby the power consumption conveniently varies from 0.83mW to 25.73mW. The die area is 1.3 * 1.2 mm2.