具有功率因數修正及減少待機耗能之數位控制交流-直流轉換器的研製

Design and Implementation of Digital-controlled AC-DC Converter with PFC and Standby Power Reduction

莊博欽(Po-Chin Chuang)

指導教授 ： 賴炎生

國立臺北科技大學/電資學院/電機工程系所/碩士(2008年)

https://doi.org/10.6841/NTUT.2008.00236

摘要

本論文主要研製一待機耗瓦符合綠色能源規範之數位控制交流-直流轉換器。本論文的貢獻為設計一低耗瓦之啟動電路，並提出ㄧ判別待機方法，藉此減少待機能源消耗，並符合綠色能源規範。本文所研製之數位電源轉換器的詳細規格如下：
額定功率：100瓦
額定輸入電壓：交流100伏~120伏 (額定為110伏)
額定輸出電壓：直流24伏
無載耗瓦：低於0.5瓦(不含FPGA Power)
功率因數：滿載條件下，功因高於0.95
實驗結果係以Xilinx® FPGA基礎之控制系統來設計與實現，由實驗結果顯示在滿載輸出時之輸入功率因數可達到0.996以上；此外，亦可滿足待機功率消耗小於0.5 W之綠色能源規範需求。

關鍵字

功率因數校正 ； 待機能源 ； 交流-直流轉換器

並列摘要

The objective of this thesis is to design and implement a digital-controlled AC-DC converter which meets the green power specifications under standby condition. The contributions of this thesis are to design a low power consumption of start circuit, and presents a method to identify standby condition. It will significantly reduce the standby power to meet the energy code. The specifications of digital-controlled converter are as follows:
Power rating: 100W
Input voltage rating: AC 100~120 V (nominate value = 110 V)
Out voltage rating: DC 24V
No load power consumption: < 0.5 W (without including FPGA power)
Power factor: > 0.95 at full load
The digital controller of AC-DC converter is implemented using Xilinx® FPGA-based board. It has been demonstrated that the input power factor is greater than 99.6 % in the whole voltage range and full load condition. The power consumption under standby condition is less than 0.5 W confirming the design and implementation.

並列關鍵字

Power factor correction (PFC) ； Standby power ； AC-DC converter

參考文獻

[1] 商周出版編輯室，「全球暖化，臺灣該怎麼辦?」，全國新書資訊月刊，2007，第9-12頁。

[7] Standby power use and the IEA “1-watt plan” – fact sheet, International Energy Agency, 2007.

[8] International electrotechnical commission, http://www.iec.ch/index.html, 2007.

[10] 方志行、謝文考，「家庭電器的待機電力發展趨勢」，台灣區電機電子工業同業公會，2001。

[15] 黃柏騰，符合待機規範之交流/直流轉換器之研製，碩士論文，國立台北科技大學電機工程系碩士班，台北，2006。