蕭特基快閃記憶體之設計與模擬

Design and Simulation of Schottky Barrier Flash Memory

羅彥翔(Yan-Xiang Luo)

指導教授 ： 施君興

元智大學/電機通訊學院/電機工程學系/碩士(2009年)

https://doi.org/10.6838/YZU.2009.00270

摘要

浮動閘式快閃記憶體近年來已為主流的非揮發性半導體記憶體，但在元件尺寸微縮下，遇到使用偏壓過高與熱電子寫入效率不佳等問題。本文利用二維元件模擬，探討新式蕭特基能障快閃記憶體的寫入特性，並研究各種元件架構對其寫入特性之影響。蕭特基能障快閃記憶體因在源極/通道介面上具有蕭特基能障之特點，有別於傳統的浮動閘式元件，其具備源極端熱電子注入之寫入特性，可加強熱電子效應並在較低的操作偏壓下，提高寫入的閘極電流。另一方面，使用雙功函數閘極、摻雜分離層以及SOI(Silicon-On-Insulator)基板，亦能進一步的提高寫入時的閘極電流，有效解決使用偏壓過高與熱電子寫入效率不佳等問題。

關鍵字

蕭特基能障、快閃記憶體，熱電子

並列摘要

The standard floating gate Flash cells is the mainstream nonvolatile semiconductor memory. The challenges to future scaling are imposed by the non-scalable tunneling oxide and high voltage to provide sufficient drain-side hot electron injections. This study uses two-dimensional device simulator to present a novel Schottky barrier source/drain Flash memory cell with promising source-side hot electron injection. Rather than conventional cell, the unique Schottky barrier formed at source/channel interface significantly promotes the amount of source-side hot electrons to provide high injection efficiency at considerably low voltages without compromising between gate and drain biases. An optimal design of Schottky Barrier Flash cell is achieved using the dopant segregation layer, silicon-on-insulator substrate and dual workfunction gate with enhanced gate current.

並列關鍵字

Schottky Barrier, Flash Memory, Hot Electron

參考文獻

[7] G. Atwood, ‘‘Future Directions and Challenges for Etox Flash Memory Scaling,’’

2004, pp.301-305.

[8] A. T. Wu, T. Y. Chan, P. K. Ko and C. Hu, “A source-side injection erasable programmable read-only-memory (SI-EPROM) device,” IEEE Electron Device Letters,Volume 7, Issue 9, Sep 1986, pp. 540-542.

[9] W. T. Chu, H. H. Lin, C. T. Hsieh, H. C. Sung, Y. H. Wang, Y. T. Lin and C. S. Wang, “Shrinkable triple self-aligned field-enhanced split-gate flash memory,” IEEE Transactions on Electron Devices, Volume 51, Issue 10, Oct. 2004, pp.1667-1671.

[10] C. Y. S. Cho, M. J. Chen, C. F. Chen, P. Tuntasood, D. T. Fan and T. Y. Liu, “A novel self-aligned highly reliable sidewall split-gate flash memory,” IEEE Transactions on Electron Devices, Volume 53, Issue 3, March 2006, pp. 465-473.