以矽載板為中介層的三維晶片佈局規劃及訊號分配

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

張閔盛(Min-Sheng Chang)

指導教授 ： 王廷基

國立清華大學/電機資訊學院/資訊工程學系/碩士(2013年)

https://doi.org/10.6843/NTHU.2013.00044

摘要

所謂的三維晶片(3D ICs)是將傳統二維晶片以垂直的方式堆疊起來所形成的。三維晶片是目前晶片發展的趨勢，但三維晶片的設計上面臨了許多問題，而製程上也比傳統二維晶片來得困難很多。因此，發展出了一種以矽載板為中介層的三維晶片(Interposer-based 3D ICs或稱為2.5D ICs)。這種2.5D ICs是將傳統二維晶片以水平的方式擺放在一個矽載板(interposer)上，晶片和晶片間的訊號全藉由矽載板來傳遞。
在2.5D ICs的設計中，晶片的佈局規劃以及訊號分配是非常重要的，因為不好的晶片佈局規劃以及不好的訊號分配，會影響晶片繞線的長度，甚至會產生過長的繞線，而這些過長的繞線，會讓晶片的效能變差。而這篇論文就是來討論以及解決2.5D ICs的晶片佈局規劃同時考慮訊號分配的問題。
在這篇論文中，我們提出了一個窮舉式的佈局規劃演算法(EFA)來解決2.5D ICs的晶片佈局規劃同時將訊號分配考慮進來。我們也提出了一個演算法(MCMF)來解決2.5D ICs的訊號分配問題。為了加速這兩的演算法(EFA和MCMF)，我們提出了一些加速的技巧，來讓我們的演算法更有效率。
由實驗結果看來，我們的演算法在加上一些加速的技巧，能夠有效率的解決2.5D ICs的晶片佈局規劃以及訊號的分配。

關鍵字

中介層 ； 訊號分配 ； 佈局規劃 ； 三維晶片

並列摘要

Since the implementation of 3D ICs is problematic, interposer-based 3D ICs (or known as 2.5D ICs), using a silicon interposer as an interface between a package and dies, has been seen as an alternative approach to 3D ICs. In a 2.5D IC, the floorplan of dies on the interposer and the signal assignment of macro-bumps and TSVs would impact the routing wirelength. Because overlong routing wirelength would degrade the performance of 2.5D ICs and cause timing violations, the die floorplanning and signal assignment problems for 2.5D ICs are critical. In this thesis, we propose an enumeration-based floorplanning algorithm (EFA) to solve the signal-aware die floorplanning problem (SDFP), and we solve a signal assignment problem (SAP) for micro-bumps and TSVs by a min-cost max-flow (MCMF) algorithm. To speed up the EFA and the min-cost max-flow algorithm, we also present several acceleration techniques. The experimental results show that the proposed floorplanning and signal assignment algorithms are effective and the speedup is significant when the proposed acceleration techniques are used.

並列關鍵字

2.5D ICs ； 3D ICs ； Interposer ； Signal Assignment ； Floorplanning

參考文獻

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