降低以矽載板為中介層的三維晶片佈局規劃及訊號分配的線長

On Reducing Wirelength in Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

黃偉哲(Wei-Che Huang)

指導教授 ： 王廷基

國立清華大學/電機資訊學院/資訊工程學系/碩士(2014年)

https://doi.org/10.6843/NTHU.2014.00634

摘要

由於真實的3維晶片(True 3D ICs)的製作面臨到許多的問題，一種以矽載板為中介層的三圍晶片(Interposer-based 3D ICs 或稱為2.5D ICs)成了另一種三維晶片的選擇。晶片的繞線長度和晶片的效能有著密切的關係，而晶片的佈局規劃(floorplanning)和訊號分配(signal assignment)是影響繞線長度的重要因素，因此本篇論文的目的就是要降低晶片的繞線長度。
在這篇論文中，我們考量到了從晶片層到印刷電路板(PCB)的所有內部訊號連線，用線性規劃演算法對矽載板上的晶片做漸進式佈局規劃以及用min-cost max-flow演算法對微凸塊(micro bumps)和直通矽晶穿孔(TSVs)的訊號來重新分配，並提出一個優化流程反覆地改進繞線長。由實驗結果可看出我們提出的流程確實降低了整體的繞線長度。

關鍵字

矽載板 ； 佈局規劃 ； 訊號分配 ； 線長

並列摘要

Since the implementation of true 3D ICs is still problematic, interposer-based 3D ICs (or known as 2.5D ICs) has been seen as an alternative approach. In a 2.5D IC, the floorplan of dies on the interposer and the signal assignment of macro-bumps and TSVs would impact the routing wirelength, and therefore die floorplanning and signal assignment are critical problems for 2.5D ICs. In this thesis, we focus on reducing wirelength and consider all the interconnects from the chip level to the package and PCB levels. We perform our optimization flow that iteratively performs incremental floorplanning to adjust the positions of dies on the interposer by a linear-programming algorithm and signal reassignment for micro-bumps and TSVs by a min-cost max-flow algorithm until no more improvement on wirelength. The experimental results show that the proposed flow indeed help further reduce the total wirelength.

並列關鍵字

interposer ； floorplan ； signal assignment ； wirelength

參考文獻

[2] Y.-K. Ho and Y.-W. Chang, “Multiple chip planning for chip-interposer codesign”, in Proc. of DAC, 2013, pp. 1-6.

[4] D. H. Kim, K. Athikulwongse, and S. K. Lim, "A study of Through-Silicon-Via impact on the 3D stacked IC layout," in Proc. of ICCAD, 2009, pp. 674-680.

[5] J. Cong, G. Luo, J. Wei and Y. Zhang , “Thermal-aware 3D IC placement via transformation”, in Pro. ASP-DAC, 2007, pp.780-785.

[6] W.-H. Liu, M.-S. Chang, and T.-C. Wang, “Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs”, to appear in Proc. of DAC, 2014.

[7] X. Tang et al, “Minimizing wire length in floorplanning,” IEEE TCAD, 25(9), pp. 1744-1753, 2006.