具有極佳的電磁干擾效應衰減效果之全數位展頻時脈產生器

近年來，電磁干擾的議題越來越被重視。原因在於現今高速傳輸之電路通常會產生嚴重的電磁干擾，並容易影響周遭電路之運作。因此，為了防範電子產品中所衍生出來的電磁干擾，目前已有數種電子傳輸介面制訂相關規格以防制過於嚴重的電磁干擾，例如DisplayPort等數位顯示介面。在本論文中，我們提出具有極佳電磁干擾效應衰減效果之全數位展頻時脈產生器。此全數位展頻時脈產生器可以達到真實展頻量之要求。此外，為了防止在展頻時遭遇製程、電壓、以及溫度變化而導致中心頻率偏移，我們以兩種不同版本之機制來維持頻率穩定度，其一為快速鎖定機制，另一機制為以計數器為基底來穩定頻率。此快速鎖定之全數位展頻時脈產生器使用90奈米製程之標準元件庫實現，其運作電路之面積為200m × 200m。由量測結果得知，在270MHz頻率之電磁干擾效應衰減量於0.5%與2%之展頻量分別為14.64dB以及19.69dB。此外，該電路以1.0V電壓於270MHz頻率下之功率消耗為443W。另一版本之電路為以計數器為基底之全數位展頻時脈產生器。該電路之運作面積為85m × 85m並以65奈米製程之標準元件庫實現。其模擬之電磁干擾效應衰減量各以270MHz及162MHz作用頻率於0.5%與1.5%之展頻量分別為13.99dB與20.23dB。此電路以1.0V電壓於270MHz頻率下之功率消耗為163.9W。另外，此兩版電路因為是以標準元件所設計而成，因此可以輕易的移植至不同製程，所以本論文所提出之全數位展頻時脈產生器非常適合應用於現今之系統晶片。

關鍵字

展頻時脈產生器；全數位鎖相迴路；電磁干擾

並列摘要

In recent years, electromagnetic interference (EMI) problem is more and more popular. High speed transmission usually causes severe EMI, and that will influence the operation of neighbor circuits. Therefore, there are several devices have defined the specifications to restrict the EMI, such as DisplayPort which is a digital display interface. In this thesis, an all-digital spread spectrum clock generator (ADSSCG) with high EMI reduction performance is presented. The proposed ADSSCG can provide a truly programmable spreading ratio. In order to maintain the frequency stability while performing triangular modulation, two frequency maintenance mechanisms are proposed to overcome the process, voltage, and temperature (PVT) variations. We proposed two versions of ADSSCG in this thesis, the fast-relocked ADSSCG and counter based ADSSCG. The proposed fast-relocked ADSSCG is implemented in a standard performance 90nm CMOS process, and the active area is 200m × 200m. The experimental results show that the EMI reduction is 14.61dB with 0.5% spreading ratio and 19.69dB with 2% spreading ratio at 270MHz. The power consumption is 443W at 270MHz with 1.0V power supply. The other version is the counter-based ADSSCG. The active area is 85m × 85m with a standard performance 65nm CMOS process. The EMI reduction is 13.99dB with 0.5% spreading ratio at 270MHz and 20.23dB with 1.5% spreading ratio at 162MHz. For the power dissipation, it consumes 163.9W at 270MHz with 1.0V power supply. Moreover, these two versions are designed with standard cells, and this approach can be ported to different processes very easily, and it’s very suitable in system-on-chip (SoC) era.

並列關鍵字

Spread-Spectrum Clock Generator ； All-Digital Phase-Locked Loop ； EMI Reduction ； Monotonic DCO

參考文獻

[8] Hong-Yi Huang, Sheng-Feng Ho, and Li-Wei Huang, “A 64-MHz~1920-MHz Programmable Spread-Spectrum Clock Generator,” in Proceeding of IEEE International Symposium on Circuits and Systems, vol. 4, pp. 3363-3366, May 2005.

[18] Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio Giuseppe Maria Strollo, and Claudio Parrella, “A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1048-1060, May 2010.

[1] Video Electronics Standards Association, “VESA DisplayPort Standard Version 1.1a,” Jan. 2008.

[2] Toshio Sudo, Hideki Sasaki, Norio Masuda, and Jams L. Drewniak, “Electromagnetic Interference (EMI) of System-on-Package (SOP),” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 304-314, May 2004.

[4] Soon-Kyun Shin, Seok-Min Jung, Jin-Ho Seo, Myeong-Lyong Ko, and Jae-Whui Kim, “A slew-rate controlled output driver using PLL as compensation circuit,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1227-1233, Jul. 2003.

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具有極佳的電磁干擾效應衰減效果之全數位展頻時脈產生器

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