- 學位論文
DSTTD多天線系統下QR分解預處理之硬體架構設計與實現
Hardware Architecture Design and Realization of the Preprocessing QR-decomposition for DSTTD-MIMO Communication System
摘要
近幾年以來多輸入多輸出 (Multiple Input Multiple Output,MIMO) 技術的使用逐漸廣泛，各種不同的規範也因應而生，其中之一是目前當紅的3GPP-LTE (3GPP Long Term Evolution)。 3GPP-LTE結合了正交分頻多工 (Orthogonal Frequency Division Multiplexing,OFDM) 的技術以及2X2和4X4 MIMO的分集天線技術規格，同時支援頻分雙工 (Frequency Division Duplex,FDD)和時分雙工(Time Division Duplex,TDD)。本篇論文選擇了雙空時傳輸分集 (Double Space-Time Transmit Diversity,DSTTD) 架構，並在此種架構之下，進行檢測 (detection) 端的預處理 (Preprocessing) 動作。在MIMO系統之中，檢測佔了很重要一部份，而有些檢測器則會結合QR 分解的運算，如連續干擾消除 (Successive Interference Cancellation,SIC) 檢測器ma K-best 檢測器等。本論文於4X2 DSTTD架構下實現其前端電路預處理的部份。預處理的部分使用了Givens Rotation 演算法來進行QR分解 (QR Decomposition) 的動作，並且以CORDIC (COordinate Rotation DIgital Computer) 演算法來實現。然而於DSTTD架構之下，所求得的矩陣有其特殊性，本論文利用此特性對Givens Rotation 演算法執行優化的動作，進而達到優化硬體架構實現的目的。有關於硬體實現的部份，首先利用Matlab軟體進行優化演算法以及進行驗證，再使用Xilinx ISE 12.2進行Verilog code 的程式撰寫。透過Xilinx ISE 12.2內建之函數驗證(function verification) 來確認結果之正確性，最後以Virtex4系列中型號為xc4vlx100-12ff1148的FPGA 模擬板來進行電路合成(synthesis) 。合成結果中，預處理的部份總共佔用了2304k個Slices，而最大操作頻率則為137.778MHz。
並列摘要
In recent years, the multiple input multiple output (MIMO) technique has been adopted by several important wireless communication industrial standards. One of these standards is the 3GPP Long Term Evolution (3GPP-LTE) standard. The 3GPP-LTE standard combines the orthogonal frequency division Multiplexing (OFDM) and MIMO techniques with 2-by-2 and 4-by-4 antenna configurations. It also supports the frequency division duplex (FDD) and time division duplex (TDD) transmission at the same time. In this thesis, signal detection for one of the MIMO techniques, the double space-time transmit diversity (D-STTD) system, is studied. Important detection schemes include Successive Interference Cancellation (SIC) detector, K-best detector, …, etc. These detection schemes require QR-decomposition (QRD) at their preprocessing stage. In this thesis, the Givens rotation based QRD for the detection of D-STTD signals is implemented using the coordinate rotation digital computer (CORDIC) hardware. One specialty about the D-STTD signal is that the channel matrix is comprised of 2-by-2 Alamouti submatrices. This property allow us to develop hardware with low cost. For the design procedure, MATLAB simulations are executed to verify the detection algorithm. Xilinx ISE 12.2 built-in function is used to verify the correctness of our designed circuit function. The Virtex4 xc4vlx100-12ff148 FPGA board is selected for synthesis. The synthesis results reveal that our designed preprocessing circuits requires 2304 slices and can work with maximum frequency 137.778 MHz.