- 學位論文
反相及同相注入耦合C級振盪器之設計與比較
Design and Comparison of Anti-Phase and In-Phase Coupling Class-C QVCO
摘要
在無線通訊系統中，振盪器是不可或缺的元件之一。隨著製程不斷地進步，射頻積體電路可被整合在系統單晶片中，電晶體的大小快速縮小且操作速度更快，使晶片中可以容納更多功能，但被動元件的效能並未能有效地隨著製程進步而提升，例如，目前振盪器的效能仍受限於被動元件(電感及電容)的品質因素(Quality factor)。傳統的振盪器架構並無法滿足更先進的系統要求，通常，為了獲得更低的相位雜訊，導致更高的功耗消耗及更複雜的架構，因此本論文提出了新的振盪器電路架構，於有限的功率下能有效地降低相位雜訊。 一般射頻收發機，為了要抑制鏡像頻率所造成的效能下降，會採用正交升頻/降頻的架構，本論文首先設計一個2.4GHz低相位雜訊之四相位壓控振盪器。其中振盪器部份的設計採用Class-C的壓控振盪器架構。相較於傳統的架構，Class-C的架構會減提升電晶體操作在飽和區的時間比例，使得相位雜訊得到一定程度的改善。然而卻有不易起振的情形。 在這篇論文中，我們提出一個新的互補式架構以提高Class-C正交壓控振盪器相位誤差和相位雜訊的效能，在不大幅增加功率的情況下，增加迴路增益。 此外，本架構採用同相注入耦合機制具有更小的跨耦合電晶體DC值和較低的均方根有效ISF的平方值（rms），相較於一般並聯耦合振盪器，有較少的升頻/降頻閃爍雜訊。 在本論文中，我們推導出一個最佳的耦合係數用以取捨相位誤差及相位雜訊的效能，為了證明此概念，我們使用台積電0.18m CMOS製程加以驗證，在1.8V的電源供應下功率消耗僅3.04mW，且在距離中心頻率1MHz之相位雜訊可達-131.38dBc/Hz，FOM為-194.23dB/Hz。此四相位振盪器架構適用於低功耗射頻收發器及高效能時脈產生器。
並列摘要
Oscillator is a critical component in a wireless communication system. As continuous CMOS process scaling, complex RF communication system can be integrated in single silicon chip. However, the performance of passive components does not improve effectively with the process advances. For example, oscillator performance is still limited by quality factors of passive components (inductors and capacitors). Conventional oscillator can’t satisfy the specification of advanced communication system. Thus, to achieve low phase noise, oscillator usually requires large power consumption and complicated architecture. In the thesis, we proposed a new architecture to improve phase noise while consuming limited power consumption. In a heterogeneous communication system, interference at the image frequency can deteriorate performance of a communication system. Therefore, quadrature down/up conversion architecture is widely used to suppress the effect from interference at the image frequency. In general, Class-C oscillator was adopted in the core of oscillator. It can provide a superior phase noise performance at low power consumption while comparing to conventional LC oscillator. However, it has the weak start-up condition. The thesis presents a novel complimentary Class-C type QVCO to reduce both phase noise and phase errors. It also increases loop gain in the case without substantial enhancement of power. The in-phase injection-coupling mechanism has much smaller DC value across the coupling transistors and lower root mean square (rms) value of the effective ISF, thus resulting in less flicker noise up-conversion and lower far-from-carrier noise than the conventional anti-phase coupling mechanism. In the thesis, we derived the optimal coupling factor to trade off phase error and phase noise. To prove the concept, the proposed IPIC-QVCO was fabricated using TSMC 0.18μm CMOS technology. The design achieves -131.38dBc/Hz at 1MHz offsets, and a remarkable figure-of-merit (FOM) of -194dB/Hz over wide ranges of temperature and frequency while consuming 3.04mW. The proposed QVCO architecture is suitable for low-power RF transceiver and high-performance clock generation.