An Experimental Investigation on Silicon Wafer Thinning Process

本文應用系統性的實驗方法，針對矽晶圓薄化製程技術進行研究，並利用田口實驗方法探求最適的製程參數。為發展快速有效的批次式薄化技術，本研究透過適當的蝕刻撰擇、配方調控及製程參數的控制，在研磨薄化製程後運用批次式蝕刻技術將晶圓繼續薄化50μm，並就其可行性及問題進行探討。本研究中使用的製程及參數，可成功達成將8吋矽晶圓厚度薄化至100 μm、50 μm及25 μm的目標。

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並列摘要

With an increasing demand of thinner chips and the stacked-die packages, backside thinning of fully processed IC wafers has become a widely used technique in advanced semiconductor manufacturing. In this paper, a systematic experimental study on silicon wafer thinning process was made with the proposed thinning procedure. A series of experiments were conducted with the Taguchi method to obtain the thinning parameters that could successfully reduce wafer thickness by 50 μm after the grinding process. Also other experiments were performed to investigate the feasibility and associated problems of wafer thinning process in batch type. The eight-inch silicon wafers thinned down to 100 μm, 50 μm and 25 μm levels using this process have been achieved (Figure 1) in this study.

並列關鍵字

silicon wafer ； backside thinning ； wet etching ； batch process

國際替代計量

An Experimental Investigation on Silicon Wafer Thinning Process

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