A Scalable Electrical Model for 3D IC with Through-Silicon Via

Mei-Ling Wu ； You-Yi Chen

《中國機械工程學刊》 37卷6期 (2016/12) Pp. 635-645

摘要

The scalable electrical model of a through-silicon via (TSV) is proposed in this work. Development of a 3-D IC integrated circuit is believed to be key to achieving smaller circuits with increased functionality for electronic products. While arrays of TSVs are required in a 3-D IC, the crosstalk, which is the interaction of the electric and magnetic fields of a TSV with adjacent TSVs, is an important issue. Based on the proposed model, we analyze the electrical behaviors of a TSV with geometrical parameter variations in the frequency domain. According to the frequency domain analysis, the parasitic capacitance is an important factor that changes with TSV shape for signal integrity. The analytic equations of this model are derived from the physical configuration. For this equivalent circuit model, the analytic equations include the parameters of the structural geometry and the material properties as variables. We discuss not only the return loss and insertion loss but also the far end crosstalk and near end crosstalk. According to the simulation results, the power attenuation in a TSV array model is worse than for a TSV pair and the influence of crosstalk is still acceptable.

關鍵字

Through Silicon Via ； S-parameter ； power dissipation ； signal integrity