An Efficient Architecture of Extended Linear Interpolation for Image Processing

林正基(Chung-Chi Lin) ； 許明華(Ming-Hwa Sheu) ； 江煥鏗(Huann-Keng Chiang) ； 廖啓賢(Chishyan Liaw) ； 吳曾傅(Zeng-Chuan Wu) ； 蔡文凱(Wen-Kai Tsai)

《Journal of Information Science and Engineering》 26卷2期 (2010/03) Pp. 631-648

https://doi.org/10.6688/JISE.2010.26.2.18

並列摘要

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost and high-speed architecture with interpolation quality compatible to that of bi-cubic convolution interpolation. The method of reducing computational complexity of generating weighting coefficients is proposed. Based on the approach, the efficient hardware architecture is designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The architecture is implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13μm standard cell library. The simulation results demonstrate that the efficient VLSI of extended linear interpolation at 267MHz with 25980 gates in a 450 × 450μm^2 chip is able to process digital image scaling for HDTV in real-time.

並列關鍵字

interpolation ； scaling ； image reconstruction ； bi-cubic convolution ； VLSI