Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems

Nowadays, the hardware of field programmable gate arrays (FPGAs) can be reconfigured both dynamically and partially. A dynamically and partially reconfigurable system can share hardware contexts among various hardware tasks. However, such FPGA systems require much memory to save the hardware context. To solve this problem, this work proposes a methodology for switching hardware context in dynamically partially reconfigurable FPGA systems. This method can reduce the reconfiguration time and memory size of hardware context-switching by analyzing the characteristic of bit indexes and frame addresses. The experimental results show that the proposed method reduces 10.674% in hardware reconfiguration time, 47.47% in memory size, and 41.25% in resource overhead.

並列關鍵字

context-switching ； dynamically partially reconfigurable system ； Readback ； reconfiguration time ； memory size ； resource overhead

被引用紀錄

曾筱君（2010）。可重組系統之通用型硬體內文儲存設計〔碩士論文，國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2010.00130

黃湧焜（2008）。動態部分自我可重組系統之硬體內文切換方法〔碩士論文，國立臺北科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0006-3107200808172600

國際替代計量

Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems

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