可重組系統之通用型硬體內文儲存設計

Adaptive Hardware Context-Switching Approach for Reconfigurable Systems

曾筱君(Shiau-Jiun Tseng)

指導教授 ： 李宗演

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2010年)

https://doi.org/10.6841/NTUT.2010.00130

摘要

目前動態可重組FPGA系統架構中，其內部可重組區域可規劃成多個硬體模組以利執行，在多重任務模組做硬體切換時，其切換的過程可重組系統需要紀錄硬體模組目前執行的狀態及資料儲存的暫存器位址，並且使用大量的記憶體來儲存硬體之內文，由於在回存的過程中，硬體模組切換的時間若是過長則會影響整體系統的效能。另外，可重組FPGA硬體架構因不同的型號及版本各有其特色，大部份的研究只針對單一版本硬體內文儲存做處理，而難以廣泛應用。因此本論文提出一個通用型硬體內文儲存方法，其中建立模組資料庫，並以選擇性Frame回讀機制來記錄使用的硬體內文資料，所使用的內文儲存位元格式，可以廣泛適用於Xilinx Virtex-2、Virtex-4和Virtex-5硬體架構，優點為減少儲存模組時所重覆記錄的Frame位址和位元索引參數。論文中以五個設計案例，其分別為七段顯示之上數計數器、最大公因數、資料加密、紅綠燈和離散餘弦轉換，分別驗證本方法。由實驗結果得知，本方法平均可降低56.5%的記憶體空間及53.26%的指令空間，並節省16.52%Frame讀取的時間、22.89%指令設置時間及20.5%重新配置的時間。

關鍵字

動態部分可重組 ； 硬體內文 ； FPGA ； 回讀

並列摘要

Nowadays, the ability of dynamic reconfigurable in FPGA architecture has gain its importance while switching on hardware modules. But for recent researches on reconfigurable architecture, most of them aim at one specific version. It’s inconvenient by adding additional hardware circuits to apply on all the versions. Therefore, we propose an adaptive hardware context-switching approach for reconfigurable systems. Accompany with the general bit saving format, it suits all types of Xilinx Virtex-2, Virtex-4 and Virtex-5. Which can reduces the saving number of saved frame address and bit-index. Five example designs, such as up-counter, 32-bit greatest common divisor, data encryption standard, traffic light control and discrete cosine transform are applied to the proposed method. The experimental results shown that our proposed method reduces 56.5% in memory space and 53.26% in instruction space, 16.52% less reading time of frame, 20.5% less hardware reconfiguration time and 22.89% less readback command setting time on saving hardware context.

並列關鍵字

dynamic self reconfigurable system ； hardware context ； FPGA ； readback

參考文獻

[2] Xilinx, Inc. “Development system reference guide,”

[6] M. Song, S. H. Hong, and Y. Chung, “Reducing the overhead of real-time operating system through reconfigurable hardware,” in Proc. of the 10th Euromicro Conference on Digital System Design Architectures, pp. 311-316, August 2007.

[7] C.-H. Huang, S.-S. Chang, and P.-A. Hsiung, “Generic Wrapper Design for Dynamic Swappable Hardware IP in Partially Reconfigurable Systems,” International Journal of Electrical Engineering (IJEE), Vol. 14, No. 3, pp. 229-238, June 2007.

[8] M. Heubner, T. Becker, B. Grimm and J. Becker, “An FPGA run-time system for dynamical on-demand reconfiguration,” in Proc. of the 18th Parallel and Distributed Processing Symposium, pp. 454-463, Apr. 26-30, 2004.

[9] K. Paulsson, U. Vierck, M. Hubner and J. Becker, “Exploitation of the external JTAG interface for internally controlled configuration readback and self-reconfiguration of spartan 3 FPGAs,” in Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp. 304-309, April 2008.