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並列摘要


While flash-memory has been widely adopted for various embedded systems, the performance of address translation has become a critical issue for the design of flash translation layers. The aim of this paper is to improve the performance of existing designs by proposing a caching mechanism for efficient address translation. A replacement strategy with low-time complexity and low-memory requirements is proposed to cache the most recently used logical addresses. According to the experiments, the proposed method has shown its efficiency in the reducing of the address translation time.

被引用紀錄


Ho, C. C. (2016). 超大規模快閃記憶體儲存裝置之效能、模組化和可靠度技術探討 [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU201600610
Chang, H. Y. (2015). 基於三維快閃記憶體之軟體控制部分區塊抹除設計 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2015.00932
Tsai, Y. L. (2005). 可調整式之快閃記憶體管理系統 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2005.02859

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