設計適用於HMC架構之記憶體控制器快取機制

A Memory Controller Caching Mechanism for HMC Memory Architecture

陳慶融(Ching-Jung Chen)

指導教授 ： 朱守禮

中原大學/電機資訊學院/資訊工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700863

摘要

現今主流的電腦系統架構為多核心系統(Multi-core System)，此架構整合了多個處理核心，透過多個核心平行處理的能力，提高系統的吞吐量與效能。然而，記憶體子系統卻成為此類架構的效能瓶頸。近年來，為了縮短實際上記憶體與處理器之間的速度差距，多家廠商共同研發出了新型的記憶體模組－Hybrid Memory Cube (簡稱HMC)。以提升記憶體子系統之效能。
為了縮短記憶體封包在HMC記憶體模組內的傳輸時間，本研究將針對HMC記憶體架構，研發適用於HMC記憶體存取封包之HMC快取記憶體(HMC Cache Memory)機制。此快取記憶體機制將整合於HMC記憶體架構之記憶體控制器內，以縮短外部記憶體存取封包，存取HMC記憶體所需時間。此外，本研究採用MemGrid記憶體網路，以作為整合多個HMC記憶體模組之互連網路。後續的研究將探討在不同數量的HMC記憶體模組，不同快取記憶體大小，與不同的快取置換機制的效能差異。
在前述之HMC記憶體模組、MemGrid記憶體網路交換器、與HMC快取記憶體機制等架構模型設計完成後，透過不同的Benchmark實驗，可發現本研究之HMC快取記憶體機制能縮短記憶體存取時間。不同的快取記憶體大小，與快取置換方式，將會帶來不同的效能提升。不同數量的HMC記憶體模組，亦能影響記憶體存取效能。

關鍵字

HMC記憶體 ； 記憶體控制器 ； 快取機制 ； 晶片互連網路

並列摘要

A multi-core system is mainstream of the modern computer system architecture. This kind of architectures integrate many processing cores and provide the capabilities of parallel computing. The throughput and performance of the computer system are improved. However, the memory subsystem of the multicore architectures become the performance bottleneck. In recent years, many manufacturers developed a new memory architecture, Hybrid Memory Cube (HMC), to solve the performance gap between processor and memory speed, and to enhance the performance of the memory subsystem.
In order to shorten the transferring latency of memory packets in the HMC memory module, this study aims for the characteristics of HMC memory accessing, develops new HMC Cache Memory architecture for HMC memory module. The proposed cache mechanism is integrated with the memory controller of the HMC memory module, to shorten the accessing latency of HMC memory from external memory accessing packets. In addition, this study uses MemGrid memory network, to integrate multiple HMC memory modules. This study discusses the performance difference among different numbers of HMC memory modules, different cache size, and different cache replacement policies.
The mentioned HMC memory module, MemGrid memory network switch, and HMC Cache Memory are developed and modeled. Accordingly to the evaluation of several benchmarks, the proposed HMC Cache Memory architecture can shortened memory access time. The difference among cache sizes and cache replacement policies may occur different speedups. The different amount of HMC memory modules can also affect memory access time.

並列關鍵字

HMC Memory ； Memory Controller ； Cache Mechanism ； On-Chip Network

參考文獻

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