快閃記憶體控制器之軟式決策BCH解碼晶片設計

本篇論文研究背景是以目前因為在快閃記憶體(NAND架構)製程上不斷縮小，優點可以提高儲存容量和減少成本，但是隨之而來的是儲存記憶體中資料排電壓將會互相干擾會提高導致在讀寫上發生隨機錯誤位元機率升高，傳統的BCH硬式解碼也將會隨著製程不斷進步將會碰到許多解碼效益的瓶頸，所以本篇論文的目標是發展一個在以快閃記憶體傳輸規格512位元組為基礎的軟式決策解碼晶片實現。軟式解碼是以梯度下降和疊代方式尋找出最大概似度碼字，在2004年 JN提出以里德所羅門碼為背景的軟式解碼，在每次疊代更新信任度資料將會重新排列低信任度位置去尋找最大概似度碼字，目的是避免在梯度下降中的資料傳遞發生訊號錯誤機率，減低碼字發散。在本篇論文從分析和比較是在有限碼字長度底下各個軟式解碼找出最好解碼效益的軟式解碼，本篇論文選擇以BCH軟式解碼並且結合JN排序的概念做為快閃記憶體軟式解碼器。BCH-JN軟式解碼晶片實作是以0.18um製程做實現，硬體規劃是以快閃記憶體傳輸規格大小和接近浮點數的解碼效益找出定點數值所應該規劃的範圍，另外進一步我們在硬體也分析並且比較軟式解碼中的排序、高斯消去法和梯度下降法，是否有減少軟式解碼硬體運算時間和硬體複雜度的空間。

關鍵字

快閃記憶體；浮動閘干擾；軟式決策解碼；定點數值

並列摘要

This paper research background is the technology continues to scale down, the advantage of flash memory can reduce power consumption and cost of the hardware but the threshold voltage shift of one floating gate transistor can influence the threshold voltage of its neighboring floating gate transistors through parasitic capacitance coupling effect in the flash memory. The traditional BCH decoder of hard decision can’t support to better efficient of decoding in the new manufacture. The purpose is based on the NAND flash specification of the 512 bytes transmission to design a chip of soft decision decoder. The soft decision used the tanner graph and iterations to search the maximum likelihood codeword. In the 2004, JN provide the new sorting concept in the procedure of soft decision of RS code. The purpose of JN could reduce error probability of the reliability exchange in the tanner graph after Gaussian Elimination. The paper would analysis and compares the soft decision structure to find suitable decoder on the decoding efficient and code length less than 512bytes. We decided the BCH-JN decoding of soft decision in the NAND flash. On the chip design, we based on the 0.18um to plan fix point value range to simulate and compare with real value simulation. In the hardware part, we analysis and compared their operation time and complex of the sorting 、Gaussian elimination and tanner graph circuit.

並列關鍵字

NAND Flash Memory ； BCH ； JN ； SMITH ； cell-to-cell ； floating gate

參考文獻

[1] Ki-Tae Park, Myounggon Kang, Doogon Kim, Soon-Wook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Senior Member, IEEE, and Kinam Kim., A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories, IEEE Journal of solid-state circuits, vol. 43, no. 4, April 2008.

[2] Jae-Duk Lee, Member, Sung-Hoi Hur, and Jung-Dal Choi., ”Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation, IEEE Electron Device Letters, vol. 23, no. 5, May 2002.

[3] Shu Lin, D. J. Costell., Error Control Coding : Fundamentals and Applications, 3nd ed. Prentice Hall, 1983.

[4] J. Jiang and K. R. Narayanan., Iterative soft decision decoding of Reed-Solomon codes based on adaptive parity-check matrices, in Proc. Int. Symp. Inform. Theory, Chicago, Illinois, , pp.261, Jul.2004.

[6] G. D. Forney, Jr., Generalized minimum distance decoding, IEEE Trans. Inform. Theory, vol. IT-4, pp.38-39, Sep. 1954.

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快閃記憶體控制器之軟式決策BCH解碼晶片設計

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