- 期刊
- OpenAccess
High-Level Synthesis for Minimum-Area Low-Power Clock Gating
並列摘要
Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis stage. However, previous work may suffer from a large circuit area overhead on the clock control logic. In this paper, we present an ILP (integer linear programming) formulation to consider both the clock tree and the clock control logic. Our optimization goal is not only to conform to the constraint on the overall power consumption, but also to minimize the area overhead of clock control logic. Compared with previous work, benchmark data show that our approach can greatly reduce the circuit area overhead under the same constraint on the overall power consumption.
延伸閱讀
- 李秉泓（2011）。A High-Level Synthesis Approach for Minimum-Area Low-Power Gated Clock Designs〔碩士論文，中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu201100690
- 凃雯斌（2009）。Low Power Clock Gating in High Level Synthesis〔碩士論文，中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu200901076
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- Huang, S. H., & Liu, S. Z. (2003). Implementing Optimal Clock Schedule with Minimum Cost. 中原學報, 31(3), 221-231. https://doi.org/10.6358/JCYU.200309.0221
- 鄭維壬、程駿華、黃世旭（2016）。Reliability Aware Clock Selection in High-Level Synthesis。先進工程學刊，11(4)，287-294。https://www.airitilibrary.com/Article/Detail?DocID=a0000255-201610-201612190046-201612190046-287-294