低功率時鐘閘控制電路之高階合成

隨著積體電路製程技術不斷的進步，製程尺寸不斷的縮小，現在已由深次微米進入奈米階段，在整個電路晶片中，時鐘樹(Clock Tree)的功率消耗(Power Consumption)已經提高到約晶片的一半，如何降低時鐘樹的功率消耗是一件很重要的問題。在同步序向電路設計中，時鐘閘控制時鐘樹(Gated Clock Tree)已經被提出作為很有效的方法來降低功率消耗，在一開始電路合成，我們將電路功能分配到既定的功能單元(Function Units)當中，我們稱之功能單元的模組繫結(Module Binding)，不同的模組聯繫在之後的時鐘閘控制時鐘樹合成，就會造成不同的時鐘樹，以致於功率消耗並不同。若在一開始沒有考慮模組聯繫，時鐘樹功率消耗的改善仍然有限。為了在合成就找出最佳的模組聯繫，在本篇論文中，我們提出考慮模組繫結的時鐘閘控制時鐘樹合成方法。我們的方法可以在電路設計後，在時鐘樹合成前找出最佳的模組繫結的組合，之後在時鐘樹合成時找出最佳的合成組合來降低時鐘樹上的功率消耗。為了能在不同的設計階段降低時鐘樹的功率消耗，我們提出了兩套整數線性規劃(Integer Linear Programming)，分別在高階合成階段和暫存器轉移層次合成階段來降低時鐘閘控制時鐘樹的功率消耗，比起既有的繫結，我們可以更有效的降低功率消耗。

關鍵字

整數線性規劃；低功率；電子設計自動化；時鐘閘；高階合成

並列摘要

With the integrated circuit process technology advances, the process scale has now entered the deep sub-micron nano-meter regime. In a synchronous sequential circuit, the clock signal is the most active signal in the circuit. In the entire chip, the power consumption of the clock tree has increased to about half of the chip. How to reduce clock tree power consumption is a very important issue. In fact, it is very often that only a portion of the circuit is active. Therefore, in synchronous sequential circuit design, clock gating is recognized as a useful technique to reduce the power consumption. Conventionally, the clock gating is synthesized after high-level synthesis. In this thesis, we point out that the module binding in high-level synthesis has a significant impact on the power consumption of gated clock tree. Based on that observation, we use an integer linear program (ILP) to formally formulate the problem in two design levels. One is register-transfer-level and the other one is behavior-level. Our objective is to find a module binding solution so that the power consumption (of gated clock tree) can be minimized. It is noteworthy to mention that our work is the first attempt to synthesize the clock gating in the high-level synthesis stage. Benchmark data consistently show that our approach can greatly improve the existing design flow.

並列關鍵字

EDA ； Integer Linear Program ； High-Level Synthesis ； Clock Gating

參考文獻

[1] H.L. Chen, & H.M. Chen, “On Achieving Low Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study”, Proc. of IEEE International SOC Conference, pp. 203—206, 2006.

[2] G.E. Tellez, A. Farrahi, and M. Sarrafzadeh, “Activity Driven Clock Design for Low Power Circuits”, Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 62—65, 1995.

[6] J. Oh and M. Pedram, “Gated Clock Routing Minimizing the Switched Capacitances”, Proc. of IEEE/ACM Design Automation and Test in Europe, pp. 692—697, 1998.

[8] M. Donno, A. Ivaldi, L. Benini, and E. Maci, “Clock Tree Power Optimization based on RTL Clock Gating”, Proc. of IEEE/ACM Design Automation Conference, pp. 622—627, 2003.

[9] W. Shen, Y. Cai, X. Hong, and J. Hu, “Activity-Aware Register Placement for Low Power Gated Clock Tree Construction”, Proc. of IEEE Computer Society Annual Symposium on VLSI, pp. 383—388, 2007.

國際替代計量

低功率時鐘閘控制電路之高階合成

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