低功率時鐘閘控制樹設計之研究

Minimum-Power Gated Clock Tree Design

簡嘉宏(Jia-Hong Jian)

指導教授 ： 黃世旭

中原大學/工學院/電子工程研究所/碩士(2009年)

https://doi.org/10.6840/cycu200901326

摘要

近年來，隨著製程的進步，降低功率的消耗以及有效率的面積使用已經成為一個相當重要的議題，其中，以訊號所建構出來的時鐘樹的功率消耗更是受到關切。在同步序向邏輯電路裡，時鐘閘的控制一直是一個被承認能夠有效率的改善功率消耗的方法。過去的研究顯示，以排序資料流程圖 (Scheduled DFG) 和單元繫結 (Module Binding) 為基礎，定義了行動型態樣本 (Activity Patterns)，接著衍伸出了時鐘控制邏輯來降低功率，稱為行動驅動時鐘樹 (Activity Driven Clock Tree)。
這篇文章中，我們提出了一個不同於以往的時鐘閘 (Clock Gating) 控制樹設計：我們在上層的地方使用與閘 (AND gate) 而在第一層的地方使用或閘 (OR gate)，利用或閘來將上層的與閘所擁有的行動型態互相配合來組成第一層的行動型態，若是能夠只採用部份的邏輯閘所擁有的行動型態達到組成所有第一層的邏輯閘所擁有的行動型態，那麼就能大大降低上層的邏輯閘使用量，而因為上層的邏輯閘也有行動型態，那麼減少邏輯閘的數量，也能夠減少設計上所需要的控制步驟 (Control Steps)，換言之，這個方法也減少了功率上的消耗。
我們展現出的研究成果可以有效地減少邏輯閘的數量以及整個電路所需要的控制步驟。我們建議整數線性規劃 (Integer Linear Program) 方法且以我們的時鐘樹結構為基礎來導出縮小功率的時鐘閘，我們的目標在於減少邏輯閘的使用以及減少整個時鐘樹所需要的控制步驟。和之前單純只使用與閘所建置的時鐘樹比起來，我們的方法能夠有效率的改善邏輯閘的使用量以及總控制步驟的數量，這也代表了在功率消耗上面，我們有相當大的改善。

關鍵字

時鐘閘控制 ； 功率最小化 ； 整數線性規劃

並列摘要

In recent years, with technology improved, the way to reduce power consumption and efficient area using become one of the quite important issues. Among them, the way of the power consumption is to use the signal to construct the clock tree. It is especially a serious concern. In synchronous sequential circuit design, clock gating is recognized as a useful technique to reduce the power consumption. A lot of research efforts have been paid, based on a scheduled data flow graph (DFG) and a module binding solution, it defines the activity patterns. Then, they derive the clock control logics, called activity driven clock tree, for low power.
In this paper, we present a novel gated clock tree design style: we use AND gates at upper levels and OR gates at bottom level. We can use the activity patterns of clock gates at upper level to compose the activity patterns of all clock gates at the bottom level. If we can use a part of activity pattern of clock gates to compose all the activity pattern of clock gates at bottom level, then we can greatly reduce clock gate number and also reduce the need of control steps when designs. In other words, we reduce the power consumption.
We show that our approach can greatly reduces the number of active control steps and clock gates. Then, we propose an integer linear program (ILP) to formally draw up the minimum-power clock-gating based on our tree structure. Our objective is to minimize the use of logic gates and reduce total control steps that the entire clock tree needed. Compared with the existing AND-gate-only clock gating, our approach can improve the number of clock gates and the entire control steps uses. It also means that we improve a lot on power consumption.

並列關鍵字

Power Minimization ； Integer Linear Program ； Clock Gating

參考文獻

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