低功率三維積體電路時鐘閘樹合成

Low-Power Gated Clock Tree Synthesis for 3D ICs

陳昱銓(Chen, Yuchuan)

指導教授 ： 林柏宏

國立中正大學/工學院/電機工程學系/碩士(2012年)

摘要

低功率消耗在時鐘網路設計是一個很重要的議題。為了減少時鐘網路的功率消耗許多技術例如將多工器取代成時鐘閘元件或是將多個一位元正反器合併成一個多位元正反器這些都是常用的方法。近年來三維積體電路利用TSV元件來傳遞不同層的時鐘訊號來減少線長和降低寄生元件，但是TSV使用太多對於電路會造成負面的影響，過多的TSV會造成到電路繞線擁擠以及元件擺放空間減少。因此，如何在繞線長度以及TSV的使用數量上取得權衡是必要的。根據上述，我們動機是利用三維積體電路並使用時鐘閘元件來建構我們的零歪斜三維積體電路時鐘閘樹合成。不同於之前的研究我們提出的演算法稱3D-ZGCT，利用下列步驟來減少動態功率消耗:(a)多階層群集架構(從上至下線長考量分割電路，從下至上行為驅動群集各元件)，(b)零歪斜繞線時考慮繞線長度和TSV使用量的權衡來實現零歪斜三維時鐘閘樹合成。實驗結果顯示我們的演算法非常有效率以及高效能的降低整體電路的功率消耗。

關鍵字

零歪斜 ； 直通矽晶穿孔 ； 低功率 ； 三維積體電路 ； 時鐘閘 ； 時鐘樹合成

並列摘要

Low-power play a key role of clock network design. To saved dynamic power in clock network design the technologies such as used clock gating cell replace multiplexers or merge several single-bit flip-flops into one multi-bit flip-flop are usual method. In the recent years, three dimensional integrated circuits (3D ICs) design used Through-Silicon Via (TSV) to deliver clock signal, it can reduce the interconnect wirelength and minimum the parasitic element, but more TSVs have some negative impact, like routing congestion and cell placement space have been decrease. Therefore, trade-off between wirelength and TSV usage were needed. According to above technologies, our motivation is used 3D ICs and employed the clock gating cell to construct the 3D zero skew gated clock tree. Unlike the previous works, we propose an algorithm, called 3D-ZGCT (3D Zero skew Gated Clock Tree) with the follow steps to reduce the dynamic power : (a) multilevel clustering framework(top-down wirelength-aware partition and bottom- up activity-driven clustering), (b) trade-off between wirelength and TSV counts in zero skew routing. Experimental results have shown that our approach is very effective and efficient in reducing dynamic power simultaneously.

並列關鍵字

clock tree synthesis ； clock gate ； zero skew ； low power ； 3D ICs ； TSV

參考文獻

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