基於電子系統層級設計方法之多核心系統架構改良與探索

本篇論文敘述了利用系統層級設計方法對於多核心系統所進行的架構改良與探索。我們首先分析了PAC Duo系統的效能瓶頸，並依此分別從硬體和軟體著手改善，包括降低DDR2的存取延遲，提升硬體效率，以及藉由軟體執行流程的交錯以增進軟體效率。實驗結果顯示硬體與軟體的效率改善分別達成了1.22倍與1.2倍的整體效能提升。此外，我們亦進行了與軟硬體皆有關的預先讀取(pre-fetch)改善機制，針對DDR2零散(scattered)且非連續位址資料存取的問題，藉由改變軟體流程來提升硬體存取DDR2的效率，實驗結果顯示整體效能亦有1.15倍的提升。在PAC Duo系統的基礎上，我們延伸到四核的PAC Quad系統之架構探索。平均來說，從雙核到四核的效能提升（軟體加硬體的綜合改善）相對於單核分別約為1.85倍和3.05倍。我們進行了包括增進記憶體效率以及增加硬體平行度的實驗以便能進一步提升效能，然而效能的提升卻在四核的情況下出現飽和，經由軟體的調整實驗，顯示在軟體能充分運用硬體效率的情況下，四核的效能得以再提升至3.56倍。藉由系統層級設計方法的協助，我們得以在架構探索的過程中進行軟硬體的共同最佳化。

關鍵字

電子系統層級；系統效能分析；系統架構探索

並列摘要

In this paper, we will explore the architecture design for the PAC Duo Multi-Core system based on the ESL design techniques. First, the bottleneck of system performance in the PAC Duo system will be analyzed. Various HW and SW methods including memory latency reduction and SW tasks interleaving are employed to improve system efficiency. Experimental results show that, based on the HW or SW technique, 1.22 and 1.2 times improvement on system performance can be achieved respectively. In addition, the Pre-fetch Mechanism is implemented to resolve the problem on inefficient scattered memory access. The HW memory access efficiency is increased by modifying SW operation flow and achieves 1.15 times speed-up. Based on these methodologies, we can extend the architecture exploration to four-core PAC Quad system. Basically, the performance speed-up for dual-core and quad-core over single-core is 1.85 and 3.05 times, respectively. Experimental results show that the performance improvement saturates for quad core system if we only increase memory access efficiency and HW parallelism. However, through the adjustment of SW flow, the HW efficiency can then be fully utilized and 3.56 times gain on performance can be achieved. Obviously, the HW/SW co-optimization can be achieved with the help of the ESL design techniques.

並列關鍵字

Electronic System-Level ； ESL ； System Performance Analysis ； System Architecture Exploration

國際替代計量

基於電子系統層級設計方法之多核心系統架構改良與探索

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