電子系統層級之系統功率消耗評估方法

Electronic System Level Power Estimation Methodology

薛文燦(Wen-Tsan Hsieh)

《電腦與通訊》 132期 (2010/04) Pp. 72-79

https://doi.org/10.29917/CCLTJ.201004.0011

摘要

在本篇論文中，我們提出一種電子系統層級的功率模型介面並應用至PAC Duo系統以達到快速預估系統功率消耗情形。運用此一介面，我們可以很容易地整合多樣的功率模型至電子系統層級的虛擬平台。設計者可以根據準確度及速度上的需求來選用適當的功率模型。實驗結果顯示，我們的方法可以準確地估測出系統功率消耗及其趨勢。同時，我們也運用此方法達到快速地分析不同軟、硬體架構的功率消耗行為，以證明此方法在高階架構分析上的可行性。

關鍵字

功率消耗預估 ； 電子系統層級 ； 功率模型

並列摘要

In this work, we have developed a specific power model Interface for Electronic System-Level (ESL) power estimation framework. Based on this interface, either the coarse-grained or fine-grained power models can be used according to the different requirements on the level of accuracy or computing cost. Thus heterogeneous power models can be easily integrated into the ESL virtual platform. The experimental results on our PAC Duo system show that the proposed method can accurately estimate the system power trend immediately compared with traditional methods. We also demonstrate the capability of system power and performance analysis in both hardware-view and software-view by using our approach at ESL. Meanwhile, it can be used for high level architecture exploration directly.

並列關鍵字

Power Estimation ； Electronic System-Level ； ESL ； Power Model