適用於三維堆疊晶片之邏輯層設計與驗證方法

Design and Verification Methodology for the Logic Layer of 3-D IC

黃柏涵(Po-Han Huang) ； 林煌倫(Huang-Lun Lin)

《電腦與通訊》 141期 (2011/10) Pp. 52-58

https://doi.org/10.29917/CCLTJ.201110.0008

摘要

由於計算效能的要求提升、低功率消耗的控制以及無線寬頻的普及，已帶起可攜式3C產品需求的急速攀升。因應行動多媒體終端產品需提供更高的運算能力，近日含有數位訊號處理(Digital Signal Process; DSP)能力的異質多核心應用處理器(Application Processor; AP)與軟體開發成為最佳解決方案。但考量到晶片面積越來越大會造成良率偏低，尤其多核心晶片未來IC實現與封裝的必然趨勢將會走向三維晶片(3DIC)的結構。本文將介紹3D計畫中邏輯層與記憶體堆疊之三維晶片中的邏輯層設計與驗證方法，其中將依序介紹整體架構、低功耗設計（包含電源區塊劃分、低功耗設計元件分佈以及電源操作模式）以及驗證項目與方式。

關鍵字

應用處理器 ； 平行化架構數位訊號處理器 ； 三維晶片 ； 低功耗設計 ； 異質多核心 ； 堆疊

並列摘要

Because of the need of computing performance improvement, the control of low power consumption and the popularity of wireless broadband communication, the need of portable devices raises rapidly. In order to provide higher computing capability for mobile multimedia devices, the heterogeneous multicore application processor including the capability of DSP processing with its software development environment becomes the best solution. The chip area is getting larger and larger and the yield rate is low especially for the multicore chip. 3D architecture is an inevitable trend for the realization and package of IC in the near future. This paper will introduce the design and verification methodology of logic layer, which is stacking with the SRAM layer in the 3D IC project. It contains the whole chip architecture, low power design (including the division of power domain, distribution of low power design elements and introduction of power mode) and verification suite.

並列關鍵字

Application Processor ； AP ； Parallel Architecture Core Digital Signal Processor ； PACDSP ； Three Dimension Integrated Circuit ； 3D IC ； Low Power Design ； Heterogeneous Multicore ； Stacking