從高階事務層級模型到暫存器傳輸層級設計的驗證環境建置方法

A Methodology for Building the Verification Environments from TLM to RTL

林詠捷(Yung-Chieh Lin) ； 陳奕帆(Yi-Fan Chen) ； 王逸凱(Yi-Kai Wang)

《電腦與通訊》 141期 (2011/10) Pp. 83-90

https://doi.org/10.29917/CCLTJ.201110.0012

摘要

隨著SoC系統設計的日漸複雜，為了更快速與有效率地進行系統設計，設計抽象層級將從暫存器傳輸層級(Register Transfer Level, RTL)提升至高階事務層級(Transaction Level Modeling, TLM)。因此，硬體驗證環境就相對需要能夠支援不同的層級，從高階事務層級到暫存器傳輸層級，以滿足不同待驗證設計的驗證需求。在這篇論文中，我們針對驗證環境的建置，定義了六種不同的層級的驗證階段以運用在不同的使用案例。另外，我們也提出一系列的轉接器來加速驗證階段之間的轉換。所提出的驗證方法可以用在不同的驗證環境，諸如矽智財功能性驗證、互連網路效能分析、以及晶片子系統測試。在這篇論文中，我們也以一個晶片內網路(Network-on-Chip, NoC)設計做為研究個案，證明可以實際地用在真實的系統中。驗證結果也顯示出所提的方法有助於加快不同層級下驗證環境的建置，以提升系統設計的開發速度並保證系統驗證的可靠性。

關鍵字

抽象層級 ； 驗證智財 ； 晶片內網路

並列摘要

As the SoC system design gets more complex, the design abstraction level rises from RTL to TLM to increase the efficiency of system design. Hence the hardware verification environment should support each different level, and it should satisfy the verification requirements of different DUVs from TLM to RTL. In this paper, we focus on building the verification environment, and we define six verification stages from TLM to RTL to apply to different use cases. Furthermore, we also propose a series of adapters to accelerate transition between verification stages. The proposed methodology can be applied to different verification environment such as IP functionality validation, interconnection performance analysis, and subsystem interoperability test. In this paper, we take a NoC as a study case to demonstrate our methodology can be applied to a real case in practice. And the verification result shows the proposed methodology can accelerate building the verification environment for different level, it results in the decreasing to development period of system design. It also can guarantee the reliability of system verification.

並列關鍵字

Abstraction Level ； Verification Intellectual Property ； VIP ； Network-on-Chip ； NoC