應用於低功耗能源擷取之螺旋電感迴授技術：0.5V 9GHz除小數頻率合成器

A 0.5V,9GHz Fractional Frequency Synthesizer with Spiral Feedback Technique for Low Power Energy Harvester Applications

張智翔(Chih-Hsiang Chang) ； 李瑜(Yu Lee) ； 鄭乃禎(Nai-Chen Cheng)

《電腦與通訊》 148期 (2012/12) Pp. 100-108

https://doi.org/10.29917/CCLTJ.201212.0013

摘要

近年來由於高頻與低電壓操作之時脈源需求與日俱增，有鑒於此，本論文將提出一採用新穎式倍頻與小數相位迴旋技術之頻率合成器。其中倍頻電路主要是將再生四相位壓控振盪器尾部訊號的兩倍頻率，且讓頻率合成器能達到更大輸出振幅與更高操作頻率之需求。此外，亦針對第一級除頻器與預除器提出新式折疊與相位迴旋技術，進而讓系統能於超低電壓操作條件下進行小數除頻操作。經驗證結果顯示，當系統全速度操作時，具有倍頻機制之四相位壓控振盪器與後級除法電路皆可操作於0.5伏特電源電壓，此時頻率合成器總銷耗功率約為12mW。而當載波頻率設定於9.088 GHz時，時脈相位雜訊於1MHz偏移處約-105 dBc/Hz。

關鍵字

頻率合成器 ； 壓控振盪器 ； 訊號雜訊比 ； 倍頻

並列摘要

To lower the supply voltage for high-frequency operation, a fully integrated frequency synthesizer, together with regenerative frequency-doubling and fractional phase-rotating techniques, is presented. The frequency-doubling circuit regenerates the tail signals at twice the frequency of the quadrature voltage-controlled oscillator (QVCO) to achieve larger output swing and higher operating frequency for the synthesizer. Additionally, a hybrid circuit utilizing a new folded regime for the first-stage divider and the phase-rotating circuit is developed in the prescaler. Under full -speed operation, the QVCO with the frequency doubler and the divider can work from a 0.5-V supply, whereas the synthesizer dissipates 12 mW. At 9.088 GHz carrier frequency, the measured phase noise is -105 dBc/Hz from 1 MHz offset.

並列關鍵字

frequency synthesizer ； voltage-controlled oscillator ； VCO ； signal-to-noise ratio ； SNR ； frequency doubler