5.8-GHz 頻率合成器之設計

本論文設計一個適用於無線通訊系統的5.8GHz 鎖相迴路頻率合成器。本文描述的頻率合成器包含相位頻率偵測器、電荷幫浦、迴路濾波器、LC-tank 形式的壓控震盪器、以及採用pulse-swallow 觀念但整合為單一計數器架構的的除頻器。其中電壓控制震盪器採用NMOS-PMOS 互補式架構，來得到較高的輸出振幅和較低的相位雜訊。新的雙模數除頻器架構，可以降低功率消耗及減少晶片面積。而藉由改變可程式化除頻器的輸入我們可以得到四個不同的頻道。本頻率合成器是以台積電0.18 微米CMOS 製程來設計，並經由ADS 的模擬結果證明了本頻率合成器的可行性。

關鍵字

鎖相迴路

並列摘要

This thesis designs a 5.8-GHz PLL based frequency synthesizer for wireless commutation system. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, a LC-tank VCO and a pulse-swallow architecture frequency divider with ouly one counter. The proposed LC-tank voltage-controlled oscillator adopts double cross-coupled pair in order to get larger output voltage swing and low phase noise. The new dual-modulus prescaler can decrease power consumption and reduce chip area. By regulating the appropriate value of the propose pulse-swallow divider, it can change four difference channels. The frequency synthesizer is designed by TSMC 0.18-µm single poly, six-metal CMOS process. The ADS simulation results justify the feasibility of our proposed frequency synthesizer.

並列關鍵字

PLL

參考文獻

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[5] F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. on Communications, vol. 28, pp. 1849-1858, Nov. 1980.

[6] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge

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5.8-GHz 頻率合成器之設計

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