1.5-V 5-GHz 頻率合成器

A 1.5-V 5-GHz FREQUENCY SYNTHESIZER

張嘉智(Chia-Chih Chang)

指導教授 ： 林登彬

大同大學/電機資訊學院/電機工程學系所/碩士(2004年)

摘要

使用台灣積體電路製造公司0.18-um CMOS 1P6M技術設計一個1.5-V 5-GHz基本部分為鎖相迴路的頻率合成器。我們應用整數N架構來設計頻率合成器。含有LC tank且可調至5-GHz的電壓控制振盪器構成此合成器。藉由使用新型除二電路來當作鎖相迴路之負回授路徑的第一級除頻器，而使得合成器的功率消耗減少。
此合成器共消耗功率22.5 mW，其中的8.1 mW由電壓控制振盪器與除二電路所共同消耗。相位雜訊在距離載波1 MHz處為-110 dBc/Hz。此鎖相迴路意欲應用在無線區域網路，能合成4.1 GHz至5.4 GHz的頻率。

關鍵字

頻率合成器 ； 鎖相迴路

並列摘要

A 1.5-V 5-GHz phase-locked loop (PLL) based frequency synthesizer is design in a TSMC 0.18-um CMOS 1P6M technology. We apply the integrated-N architecture to design the frequency synthesizer. The synthesizer consists of a PLL that controls a LC tank voltage-controlled oscillator (VCO) tuned at 5-GHz. The power consumption of the synthesizer is reduced by using a novel divide-by-two circuit as the first frequency divider in the PLL feedback loop.
The synthesizer consumes 22.5 mW of power of which 8.1 mW is consumed by the VCO and the divide-by-two circuit combined. The phase noise is -110 dBc/Hz at 1 MHz offset. This PLL intended for wireless LAN (WLAN) applications can synthesize frequencies between 4.1 and 5.4 GHz.

並列關鍵字

FREQUENCY SYNTHESIZER ； PLL

參考文獻

[1] H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS frequency synthesizer with an injected-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, pp. 780–787, May 2000.

[2] M. Zargari et al., “A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems,” IEEE J. Solid-State Circuits, vol. 37, pp. 1688–1694, Dec. 2002.

[4] B. Razavi, ed. Monolithic Phase-Locked Loops and Clock Recovery Circuits, Piscataway, NJ: IEEE Press, 1996.

[5] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.

[6] C. K. Chin, “Design and Realization of CMOS RF Frequency Synthesizer,” MS Thesis, Dept. of Electrical Engineering, National Taiwan University, 2000.