全積體化5.8-GHz整數-N頻率合成器

A FULLY INTEGRATED 5.8-GHZ INTEGER-N FREQUENCY SYNTHESIZER

張逸泰(Yi-Tai Chang)

指導教授 ： 林登彬

大同大學/電機資訊學院/通訊工程研究所/碩士(2004年)

摘要

這篇論文主要是用 TSMC 0.18um 1P6M CMOS 製程來分析、設計並實現一個整數-N 的頻率合成器。這個頻率合成器是設計給在U-NII頻帶中的較高頻段的接收器來使用，其架構主要包含了低功率、高效能的壓控震盪器 (VCO) 及注入鎖定式除頻器 (ILFD) 。此頻率合成器的功率消耗較低，主要是因為在鎖相迴路的回受路徑上使用了注入鎖定式除頻器 (ILFD) 作為第一級的除頻器。
此頻率合成器的工作範圍為 5.650~5.876GHz，能夠合成4個通道且每個通道的寬度為 20MHz。當電源為 1.8V 時，整個頻率合成器的總消耗功率為 34.02mW，而 VCO 與 ILFD 合起來僅只消耗 8.37mW。相位雜訊在距離載波 1MHz 的頻率為-112dBc/Hz。此頻率合成器具有 500KHz 的迴路頻寬而鎖定時間 (locking time) 約為 26us，適合應用於 IEEE 802.11a 無線區域網路。

關鍵字

無線區域網路 ； 頻率合成器 ； 鎖相迴路

並列摘要

In this thesis, a 5.8-GHz Integer-N frequency synthesizer is analyzed, designed and implemented in TSMC 0.18um 1P6M CMOS process. The synthesizer, which is designed for use in the upper band of U-NII receiver, consists of a low power, high efficient voltage-controlled oscillator (VCO), and an injection-locked frequency divider (ILFD). The power consumption of the synthesizer is reduced by using an ILFD as the first frequency divider in the PLL feedback loop.
The frequency synthesizer can work in 5.650~5.876GHz that can synthesize 4 channels with every channel space is 20MHz. The total power consumption of the synthesizer is 34.02mW from a single 1.8V supply. It is only 8.37mW that the power is consumed by the VCO and the ILFD combined. The phase noise is -112dBc/Hz at 1 MHz offset. The synthesizer has a bandwidth of 500KHz for a 10MHz reference and the locking time is about 26us, which is suitable for the IEEE 802.11a WLAN applications.

並列關鍵字

frequency synthesizer ； PLL ； WLAN

參考文獻

[1] H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS frequency synthesizer with an injection locked frequency divider for a 5-GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuits, Vol. 35, pp. 780-787, June 2000.

[2] Y. K. Chu, “Design of 802.11a WLAN Receiver 5GHzU-NII Band Down-Converter RFICs,” MS Thesis, Dept. of Electrical Engineering, National Cheng Kung University, 2002.

[3] T. H. Lee, Hirad Samavati, and H. R. Rategh, ”5-GHz CMOS Wireless LANs,” IEEE Transaction, Microwave Theory and Techniques, Vol. 50, No. 1, pp. 268-280, Jan. 2002.

[5] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.

[6] H. R. Rategh and T. Lee, “Superharmonic injection locked frequency dividers,” IEEE J.Solid-State Circuits, Vol. 34, pp. 813-821, June 1999.