漸進式升降電源操作邏輯技術於降低系統晶片功耗的探討

Investigation on Gradual-progress-supply-based Logic Techniques for SoC Power Reduction

龔存雄(Alex Cihun-Siyong Gong)

《電腦與通訊》 150期 (2013/04) Pp. 45-52

摘要

本文介紹低功率設計中的絕熱邏輯，探討並提出一稱為互補能量路徑絕熱邏輯（CEPAL）之改良架構。互補能量路徑絕熱邏輯（CEPAL）改良半靜態能量回復邏輯（QSERL），透過增加一組充、放電的電晶體，產生互補的充、放電路徑。其電路使用單一互補弦波、以不需要相位交錯的多級結構、輸出端有著類似傳統CMOS電路的靜態特性為特色。CEPAL比起QSERL，有效縮短了輸出端的浮接時間，並具有更好的抗漏電流能力與雜訊容忍度。本文將提出之CEPAL應用在數位電路中不可或缺的反相器上，以TSMC 0.18-um CMOS製程進行模擬，在實現CEPAL電路上，能有著相較於QSERL來說更佳的整體效能。

關鍵字

絕熱家族 ； 能量回復式邏輯 ； 低功耗技術

並列摘要

This paper examines the adiabatic logic families and discusses their improving methods for low-power design. An improved structure, called complementary energy path adiabatic logic (CEPAL) is proposed to improve the insufficiency of quasi-static energy recovery logic (QSERL). CEPAL employs additional complementary transistors, one in each of its charging and discharging paths, as compared to its QSERL counterpart, such that it can be with complementary energy paths. Moreover, the static CMOS characteristics can be achieved with two complementary sinusoidal power clocks. The strength of this work is that these two sinusoidal clocks do not require complex clocking schemes, rendering it realistic in practice. CEPAL substantially shortens the floating period of output voltage, and thus creates a better tolerance scheme to leakage and a satisfactory noise margin than its QSERL counterpart. The presented logic style was applied to the Inverter structure that is essential to the digital circuits. We studied the properties of interest by means of a 0.18-um CMOS process. It is measured that the CEPAL achieves an overall performance better than its QSERL counterpart.

並列關鍵字

Adiabatic Family ； Energy Recovery Logic ； Ultra low-power Techniques