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一可應用於寬頻高抑制力之反假像電荷域濾波器

A Charge-Domain Anti-alias Filter for High-attenuation and Wide-bandwidth Applications

摘要


本論文描述一離散反假像濾波器設計,此設計使用有效時脈控制電荷域濾波器建構,使得可以有效解決截止頻帶抑制能力與通道頻寬的相依性。於時脈控制電荷域濾波器架構中,藉由時間控制電荷緩衝器並移動電容間的電荷,可以減少所需的工作脈波數量,以至於可以非常彈性的選擇降取樣率的倍數。因此,離散反假像濾波器使用有效時脈控制電荷域濾波器建構下,可以非常彈性的選擇有限脈波反應的參數,並有利於截止頻帶抑制能力與通道頻寬的設計。此離散反假像濾波器晶片實現於90奈米CMOS數位製程。在量測條件600-MS/s的輸入時脈率與100-MS/s的輸出取樣率下,可以量測到88.86-dB的截止頻帶抑制能力、13-MHz的通道頻寬、12.2-dB的信號轉換增益、0-dBm的輸入三次諧波截止點。此晶片設計於1.36-V電壓, 總共消耗5.56-mA功率電流;晶片涵蓋類比與數位電路總共消耗了0.2-mm^2晶片面積。

並列摘要


A discrete-time (DT) anti-aliasing filter (AAF) with clock-efficient charge-domain filter (CECDF) for high attenuation and wide bandwidth was developed. By employing a charge buffer with timing control to move a sampled charge between capacitors, the proposed CECDF can reduce the number of pulses and select a decimation rate effectively. The DT AAF with CECDF hence can flexibly select the finite-impulse response (FIR) coefficients to relax the trade-off between attenuation and bandwidth. The chip was fabricated on 90-nm CMOS logical process. The proposed DT-AAF possesses 88.86-dB attenuation and 13-MHz bandwidth at a 600-MS/s input-clock rate (ICR) and a 100-MS/s output-sample rate. The measured gain and IIP3 are 12.2-dB and 0-dBm, respectively, consuming only 5.56-mA from a 1.36-V power supply. The chip area with analog and clock-logical circuits totally occupies 0.2-mm^2.

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