A Power-of-Two Variable Length DFT Processor Design for Communication Systems

應用於通訊系統之可變點數離散傅利葉轉換處理器設計

陳漢臣(Hun-Chen Chen) ； 顏瑞成(Jui-Cheng Yen) ； 范國泰(Kuo-Tai Fan) ； 洪千萬(Chien-Wan Hun)

《聯大學報》 5卷2期_下 (2008/12) Pp. 71-99

https://doi.org/10.29847/JNUU.200812.0019

摘要

本論文提出以群組分散式算術為基礎之可變點數離散傅利葉轉換處理器設計。相較於快速傅利葉轉演算法，本研究所提出之二的次方長點數離散傅利葉轉換分解法，首先利用Cooley-turkey演算法將長點數離散傅利葉轉換分解成二維較短點數之離散傅利葉轉換，於群組分散式算術實現此較短點數之離散傅利葉轉換時再利用偽迴旋疊積分解演算法對群組分散式算術進行再一次的分割，最後結合架構摺疊及記憶體分享等技術，使用所提出之低成本群組分散式算術架構進行硬體實現。與現存的長點數快速傅利葉轉相比較，所提出之可變點數離散傅利葉轉換設計，在硬體效能上，具有相當程度的競爭力。

關鍵字

可變長度離散傅利葉轉換 ； 分散式算術 ； Cooley-turkey演算法 ； 保存迴旋特性之分割

並列摘要

This paper presents a power-of-two variable length discrete Fourier transform (DFT) design using the low hardware cost distributed arithmetic (DA) approach for communication systems. The length of proposed DFT can be varied up to 4096. For algorithm factorization of the proposed DFT with long length, instead of commonly used in FFT, we first decompose the length of DFT into 2-D short length DFT by Cooley-turkey algorithm and reform the short one as cyclic convolution, and then further factorize the cyclic convolution with short length cyclic convolutions by using the pseudocirculant factorization algorithm. Regarding the hardware design, combining with the techniques of architecture folding and memory content sharing in DA architecture, a hardware efficient variable-length DFT processor is designed as well as realized for the communication systems. Compared with the existing variable-length FFT design, in additional to the feature of short latency, the proposed design can be an alternative of DFT design with competitive hardware cost under the same throughput rate.

並列關鍵字

variable length DFT ； distributed arithmetic ； Cooley-turkey ； cyclic preserving partitioning

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