適用於多輸入多輸出正交分頻多工系統的可變長度快速傅立葉轉換處理器之設計與實現

DESIGN AND IMPLEMENTATION OF VARIABLE-LENGTH FAST FOURIER TRANSFORM PROCESSORS FOR MIMO OFDM SYSTEMS

洪瑞鴻(Reui-Hung Hung)

指導教授 ： 汪順祥

大同大學/電機資訊學院/通訊工程研究所/碩士(2009年)

摘要

在本篇論文中，我們提出兩個多輸入多輸出可變長度的管道式快速傅立葉轉換處理器適用於WLAN和WiMAX系統。一個是支援WLAN系統，另一個是支援WLAN和WiMAX系統。經由研究幾種快速傅立葉轉換的演算法和比較計算的複雜度，我們選擇radix-2、radix-2/4、radix-2/4/8、和radix-2/4/8/16的mix-radix演算法，然後我們採用multiple-path delay commutator的架構有效率地實現我們的設計。由於實際上multiple-path delay commutator的架構需要比較少的暫存器和mix-radix的演算法需要比較少的複數乘法器。設計的結果證明我們提出的處理器可以達到比較高的throughput。使用UMC 0.18um CMOS製程實現，所佔面積分別為1.5162mm^2和2.5122mm^2，在可以正確提供四條路徑達到50MHz所花費的功率分別為213.9mW和511.3mW。

關鍵字

快速傅立葉轉換 ； 正交分頻多工 ； 多輸入多輸出

並列摘要

In this thesis, we propose two pipeline designs of multiple-input multiple-output (MIMO)　variable-length fast Fourier transform (FFT) processors for WLAN and WiMAX applications. One is 128/64-point FFT processor with 1-4 data sequences for IEEE 802.11n WLAN, and the other is 256/128/64-point FFT processor with 1-4 data sequences for IEEE 802.11n WLAN and IEEE 802.16 WiMAX. By investigating several FFT algorithms and comparing the computational complexity , we choose the mix-radix FFT algorithms in our designs. Moreover, we adopt the multiple-path delay commutator (MDC) architecture to efficiently realize our processors. It is due to the fact that the multiple-path delay commutator FFT architectures require fewer delay elements and the mixed-radix FFT algorithms need fewer complex multiplications. It is shown that the proposed processors can achieve high throughput for 1-4 data sequences. Using UMC 0.18um process, their area are 1.5162mm^2 and 2.5122mm^2,respectively. These two processors can correctly perform 4 data sequences FFT up to 50 MHz with 213.9 mW and 511.3 mW, respectively.

並列關鍵字

FFT ； OFDM ； MIMO

參考文獻

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