具低面積複雜度改良型多重路徑延遲回授之快速傅立葉轉換處理器設計

近年來正交分頻多工(Orthogonal Frequency Division Multiplexing；簡稱OFDM) 技術廣泛的被應用於各式通訊系統中，例如無線都會區域網路(Wireless Metropolitan Area Network；簡稱WMAN)、無線區域網路(Wireless Local Area Network；簡稱WLAN)、無線個人區域網路(Wireless Personal Area Network；簡稱WPAN) 及第四代行動通訊系統(Long Term Evolution；簡稱LTE) 等等。在第四代行動通訊系統(4G)中，更採用了由OFDM演進而來的正交分頻多工存取(Orthogonal Frequency Division Multiple Access；簡稱OFDMA) 調變技術。而快速傅立葉轉換(Fast Fourier Transform；簡稱FFT) 則是OFDM/OFDMA調變通訊系統中，所需用到的主要關鍵運算之一。由於寬頻通訊系統之規格及資料傳輸率發展趨向越來越高，使得FFT處理器之設計將面臨更多挑戰。因此，本論文針對以下主要的FFT設計，提出新的技術來解決問題: 針對降低硬體複雜度之挑戰問題，我們提出有別於傳統廣泛使用基底-4之蝶形運算單元設計，藉由所提出基底-4之記憶體排程優化設計，設計出具有P倍平行度，其中P可為任意2的冪次方，且擁有低面積複雜度(low-area complexity) 及高運算產出(throughput) 之核心處理單元(processing element；簡稱PE)。

關鍵字

快速傅立葉轉換處理器

並列摘要

Since recent decades, Orthogonal Frequency Division Multiplexing (OFDM) technique has been widely used in various communication systems, such as Wireless Metropolitan Area Network (WMAN), Wireless Local Area Network (WLAN), Wireless Personal Area Network (WPAN), the fourth generation mobile communication system (4G) and etc. Orthogonal Frequency Division Multiple Access (OFDMA), is a multi-user version of the Orthogonal Frequency Division Multiplexing (OFDM) digital modulation scheme, has been adopted in 4G system. Fast Fourier Transform (FFT) is one of the key operations in the OFDM/OFDMA based modulation communication systems. Since the specification requirement and data transmission rate of the broadband communication systems are much higher than ever, there exists more challenges to overcome. In this thesis, we propose effective solutions for significant performance improvements of FFT processor design as follows. For the challenge of reducing hardware complexity of processing element (PE), the optimized design based on Radix-4 FFT algorithm are proposed. Unlike the conventional widely-used Radix-4 design, the proposed design adopts a well-optimized addressing scheme, which can significantly reduces the area of processing element (PE). Besides, the proposed FFT architecture is applicable to any power-of-two FFT parallelism, which have low-area complexity and high-throughput features.

並列關鍵字

FFT

參考文獻

[1] R. W. Chang, “Synthesis of band-limited orthogonal signals for multichannel data transmission,” Bell Syst. Tech. J., vol. 45, pp. 1775-1796, Dec. 1966.

[2] J. W. Cooley and J. W. Turkey, “An algorithm for the machine calculation of complex Fourier series,” Math Comput., vol. 19, pp. 297-301, 1965.

[5] Y.W. Lin, H.Y. Liu, C.Y. Lee, “A 1-GS/s FFT/IFFT Processor for UWB Applications,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1726- 1735, Aug. 2005.

[6] M. Shin and Hanho Lee, “A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications,” IEEE Int. Symp. Circuits and Systems, pp. 960-963, 2008.

[7] S.N. Tang, J.W. Tsai, and T.Y. Chang, “A 2.4-GS/s FFT processor for OFDM-Based WPAN applications,” IEEE Trans. Circuits Syst. II, vol. 6, no. 57, pp. 451-455, June. 2010.

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具低面積複雜度改良型多重路徑延遲回授之快速傅立葉轉換處理器設計

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