鍺全包覆式場效電晶體之蝕刻製程與數值模擬的優化研究

Study on Optimal Etching Techniques for the Ge Gate All around Field-effect Transistors Fabrication Process and Numerical Simulation

朱俊霖 ； 羅廣禮 ； 許舒涵

《國家奈米元件實驗室奈米通訊》 21卷1期 (2014/03) Pp. 2-8

摘要

半導體工業之積體電路的尺寸越做越小，所以蝕刻製程是否能精準完成微影中預定圖案的轉移相當重要。本計畫中將用八氟環丁烷（C_4F_8）、三氟甲烷（CHF_3）、氯氣（Cl_2）和溴化氫（HBr）等相關氣體來進行矽鍺材料電漿蝕刻，探討其蝕刻率、均勻度與電漿蝕刻製程參數的關係。再利用製程參數來設計出新型3D電晶體元件，並藉由蝕刻技術來達到消除界面失配差排（Misfit Dislocations），或結合反覆式退火（Cyclic Thermal Annealing），進一步降低線差排（Threading Dislocations），使之達到高品質單晶結構，根據此結構可製作具有極佳閘級控制和電性表現的新型立體結構場效電晶體。另一方面，本計畫也將結合蒙地卡羅碰撞法（MCC, Monte Carlo Collision）與單元子法（PIC, Particle-in-Cell）的數值模擬，有效率的求解粒子軌跡與電場的耦合方程組，計算其蝕刻過程中之帶電粒子的分佈與能量，並探討其物理機制；模擬結果將與實驗數據做比對驗證，並修正初始與邊界條件及數值模型中的參數，藉此確模擬模型所獲數據的可信度。

關鍵字

乾式蝕刻 ； 電晶體元件 ； 數值模擬

並列摘要

Because the size of integrated circuits becomes smaller in the semiconductor industry, the precise pattern printed by photolithography plays an important role in etching fabrication process. In this project, several gases of C_4F_8, CHF_3, Cl_2 and HBr will be used to perform plasma etching on wafers of Ge/Si interface. There after the relevant etching rate, isotropic etching and parameters of equipments will be explored. We are going to develop a new 3D transistor by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface, or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality. Based on this structure, a new type of 3D transistor with excellent gate control capability and electrical property can be fabricated. Moreover, the Particle-in-Cell (PIC) method combined with Monte Carlo collision (MCC) will be conducted to effectively solve the coupled equations of particles' trajectories and electric field. Thus the ionized particles and their energy distributions during etching ocess can be acquired and the corresponding physical mechanism can be explored. The simulated results will be validated by experiments, therefore initial and boundary conditions as well as parameters in numerical model will be modified to enhance data reliablility.

並列關鍵字

Dry Etching ； Transistor ； Numerical Simulation