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高熱穩定度(>600 ℃)介面層的開發並整合於鍺互補式金氧半場效電晶體

Development of High Thermal Stability (> 600 ℃) Interfacial Layer for Ge CMOSFETs

摘要


本研究我們提出高熱穩定度以及低介面缺陷以二氧化鉿(HfO_2)為基底的閘極堆疊結構,其中高穩定度的介面層HfGeO_x的形成是經由成長完GeO_x之後插入一層HfO_2於常見的HfO_2/Al_2O_3/GeO_x/Ge閘極堆疊。另外我們驗證了兩種低溫成長出小於1.0 nm以下的介面層的方法,其為原處氧電漿氧化法(In Situ Plasma Oxidation, PO)與微波氧化法(Microwave Oxidation, MWO)。經由電性分析的結果我們發現插入一層HfO_2於Al_2O_3/GeO_x之間會形成一層HfGeO_x介面層,此介面層相較GeO_x介面層擁有較高的熱穩定度,以及擁有較低的閘極漏電流以及介面缺陷密度(Dit)。接著我們利用新的閘極結構HfO_2/Al_2O_3/HfO_2/GeO_x/Ge 整合在P型電晶體可得到I_(on)/I_(off)比大於10^4以及次臨界擺幅(S.S.) = 120 mV/decade;並在N 型電晶體則得到些微差的元件特性(I_(on)/I_(off) > 10^3和S.S.= 219 mV/decade)。最後利用Split C-V法量測後發現新的閘極堆疊結構可改善高電場下的遷移率(Mobility)。

並列摘要


In this paper, we demonstrated the Ge CMOSFETs with high thermal stability and low-Dit HfO_2- based gate stack. A high thermal stability interfacial layer (IL) HfGeO_x was proposed by adding an extra HfO_2 layer after GeO_x formation into a commonly used HfO_2/Al_2O_3/GeO_x/Ge gate stack. For IL study, we employed two low-temperature approaches for forming 1.0 nm IL, i.e., in situ plasma oxidation (PO) and microwave oxidation (MWO). And we observed that inserting HfO_2 into Al_2O_3/ GeO_x can form HfGeO_x IL which depicted better thermal stability (up to 600℃), low gate leakage and lower interface state density D_(it) (~ 4.8×10^(11) eV^(-1)cm^(-2)) than GeO_x. By using the new HfO_2- based gate stack, PFET showed the I_(on)/I_(off) ratio of > 10^4 and a S.S. value of 120 mV/decade; while the NFET depicted slightly worse performance with the I_(on)/I_(off) ratio of 10^3 and a S.S. value of 219 mV/decade. Further, new HfO_2-based gate stack was beneficial to improve the mobility of high-E field.

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