高介電係數閘極氧化層與矽鍺、鍺通道之介面工程應用於金氧半電晶體之製程研究

Process Study of High-k Gate Dielectric and Interface Engineering for MOSFETs with SiGe/ Ge Channel

李震謙(Li, Chen Chien)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/博士(2016年)

摘要

近年，為了持續改善金氧半電晶體元件的電特性，很多技術持續被引入金氧半電晶體元件中，包含使用含矽鍺材料的基板以及高介電常數氧化層等等，其中，為了持續微縮等效氧化層厚度，我們需要使用高介面係數氧化層來改善微縮所造成的漏電問題，但其製程熱穩定仍有待改善，而隨著元件持續微縮，通道載子遷移率卻持續下降，解決的方法之一就是使用擁有較高載子遷移率的材料，例如鍺，其電子遷移率為矽的兩倍，電洞遷移率為矽的四倍，因此很有機會應用在半導體製程上。
本論文研究如何整合矽鍺虛擬基板與高介電常數氧化層，使金氧半電晶體元件的電特性，包含臨界電壓、等效氧化層厚度以及載子遷移率等等可以進一步被改善，在矽鍺基板的比例選擇上，以含有30%較高鍺含量百分比的虛擬矽鍺基板為主，藉由堆疊氮氧化鈦與氮氧化鉭於高介電常數氧化鉿層之上來改善矽鍺電晶體之汲極電流、轉導與次臨界擺幅。此外，矽鍺通道與氮氧化鉭有很好的結合，其轉導退化特性與臨界電壓偏移特性等可靠度表現皆不錯。因此，氮氧化鉭可與矽鍺通道有良好的結合，並應用在金氧半電晶體上。
我們利用原子層化學氣相沉積系統來堆疊高介電係數氧化層，並在製程中用通入遠端電漿，在製程腔體中執行本位電漿氮化處理。經過本位電漿氮化處理後的金氧半電容元件，其等效氧化層厚度可以微縮到0.83奈米，而漏電流可以降低到1.7x10-3 A/cm2。對於可靠度量測而言，本位氨氣電漿氮化處理可以抑制定電場所誘導的平帶電壓偏移和漏電流，利用此氮化方法可以有效鈍化氧空缺以及抑制氧空缺的產生，因此本位電漿氮化處理可被視為一個很有潛力的氮化方法。
我們研究鹵素電漿在金氧半電晶體元件的介面處理對電性的影響，在金氧半電晶體元件的介面層經過鹵素電漿處理過後，氧化鉿介電層會形成四角形的晶向，此種晶向擁有較高的介電常數，因此可以得到較低的等效氧化層厚度。此外，經過氯氣電漿處理過後，可以提升載子遷移率和轉導，以及降低次臨界擺幅，因此，氯氣電漿可以有效的應用在金氧半電晶體元件的介面處理製程上。
在原子層化學氣相沉積系統中，利用水氣電漿在純鍺基板上成長氧化鍺，以此作為高介電係數氧化層與基板之間的介面層，在成長此介面層時，將整個腔體溫度升高到370°C，藉此讓介面層產生脫附效果，使二氧化鍺的成分升高，次氧化物成分降低，研究得知利用此法，氧化鍺鉿介面層內的4價鍺濃度高達95%，在電性上，可以微縮等效氧化層厚度到0.39奈米，也可以同時降低漏電流，然而，介面缺陷密度與頻率散射效應等電性仍待改善。
將氧化鋯與氧化鉿交互堆疊組成四種不同的組合，以此作為金氧半電晶體的介電層，而四種組合分別為，單層氧化鋯、單層氧化鉿、氧化鋯/氧化鉿、以及氧化鋯鉿；研究得知，具有單層氧化鋯的元件可以獲得較薄的等效氧化層厚度，但是因為其介面層品質不佳，故介面缺陷密度較高，有趣的是，以氧化鋯/氧化鉿雙層堆疊結構作為介電層，可使介面缺陷密度以及次臨界擺幅降低，而載子遷移率也可以同時提高到335 cm2/V-sec，此外，具有氧化鋯/氧化鉿雙層堆疊結構的金氧半電晶體，等效氧化層厚度可以微縮到0.62奈米，且漏電流可以降低到2x10-3 A/cm2。因此，氧化鋯/氧化鉿雙層堆疊結構非常有潛力應用在金氧半電晶體元件上。

關鍵字

半導體物理 ； 半導體製程技術 ； 金氧半電晶體

並列摘要

SiGe virtual substrate and high-k dielectrics were introduced into Metal Oxide Field Effect Transistor (MOSFET) devices to improve the electrical characteristics. For ultrathin equivalent oxide thickness (EOT), a higher-k dielectric was proposed to solve the leakage current issue. However, a reduction in carrier mobility is also encountered. A promising candidate to solve this issue is to alternate Si channel with high mobility material like Ge, which can offer two times higher electron mobility and four times higher hole mobility than Si.
MOSFET with SiGe channel and higher-k gate dielectric are studied. Samples with TaON/HfO2 or TiON/HfO2 stacks show larger drain current, transconductance, and smaller subthreshold swing than that with single HfO2 layer. In addition, the reliability for SiGe MOSFET device is clearly improved with TaON/HfO2 stacks in terms of trans-conductance degradation and Vth shifts after hot-carrier stress. The integration of SiGe channel with TaON higher-k dielectric is useful for high performance MOSFETs.
Metal oxide semiconductor (MOS) devices with in-situ remote plasma treatment during high-k dielectric deposition are studied in this thesis. The EOT value and leakage current of the MOS device with in-situ NH3 plasma treated high-k dielectrics can be significantly reduced to 0.83 nm and 1.7x10-3 A/cm2, respectively. The stress-induced flat-band voltage shifts and leakage current are obviously reduced as well. In-situ remote plasma treatment also provides a good approach of nitridation for high-k dielectrics. The oxygen vacancy can be passivated by nitrogen, which suppresses further oxygen diffusion and the formation of the oxygen vacancies. The in-situ NH3 plasma treatment is useful for high performance MOS devices with good reliability.
High-k gated MOSFETs with Cl2 and CF4 plasma treatments are studied in this thesis. A higher-k HfON with more tetragonal phase is formed by the halogen plasma treatment on interfacial layer (IL). A low inversion equivalent oxide thickness in MOSFET is obtained with the Cl2 plasma treated IL. In addition, high mobility and transconductance, and low subthreshold swing are obtained by the Cl2 plasma treatment, which therefore is a promising interface engineering for advanced MOSFETs.
Ge MOS devices with about 95% Ge4+ in HfGeOx interfacial layer are obtained by H2O plasma process together with in-situ desorption before atomic layer deposition (ALD). The EOT is scaled down to 0.39 nm; the leakage current is decreased as well. The improvement can be attributed to the in-situ Ge sub-oxide desorption process in an ALD chamber at 370 oC. The interface trap density and frequency dispersion need further process development to be reduced.
Electrical characteristics of Ge pMOSFETs with HfO2, ZrO2, ZrO2/HfO2, and HfZrOx gate dielectrics are studied in this thesis. A lower EOT is obtained in ZrO2 device, which however has a higher interface trap density (Dit) due to its inferior dielectric/Ge interface. Interestingly, the Dit and sub-threshold swing of Ge pMOSFETs are clearly reduced by ZrO2/HfO2 stack gate dielectric. A peak hole mobility of 335 cm2/V-sec is achieved in ZrO2/HfO2 device thanks to good dielectric/Ge interface. Furthermore, the EOT of ZrO2/HfO2 device is 0.62 nm, and the leakage current is 2x10-3 A/cm2. Therefore, a ZrO2/HfO2 stack gate dielectric is promising for Ge MOSFETs.

並列關鍵字

Semiconductor Physics ； Semiconductor Manufacturing Technology ； Metal Oxide Field Effect Transistor

參考文獻

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