整合新穎表面鈍化技術與結晶態高介電常數閘極介電層之高效能鍺金氧半元件

Fabrication of High-Performance Ge MOS Devices by Integrating Novel Surface Passivation and Crystalline High-κ Gate Dielectric

吳旻霖(Min-Lin Wu)

指導教授 ： 巫勇賢

國立清華大學/原子科學院/工程與系統科學系/博士(2013年)

https://doi.org/10.6843/NTHU.2013.00108

摘要

本篇論文著重在建立一個不需要使用鍺基板且相容於超大型積體電路技術的製程，並具有經濟效益的方法製作鍺金氧半場效電晶體，並解決鍺薄膜之元件整合上所遇到的問題。我們特別強調最重要的議題，維持鍺薄膜與高介電常數材料之間的高品質介面。而我們也利用結晶態取代非晶態介電層，因為結晶態氧化物具有較高的介電常數，可以在較厚的物理厚度之下，維持較低的等效氧化層厚度。
首先，我們利用在矽基板上，製作氮氧化矽為閘極介電層在鍺薄膜上，並觀察其電特性與物理特性。可以觀察到有極小的頻率散射現象與可忽略的磁滯現象，其意味著有非常少量的氧化層缺陷。並且可以有效地鈍化鍺薄膜上，其在能隙中間的介面缺陷密度為7.08×1011 cm-2 eV-1,因此可以有效地提升金氧半場效電晶體的載子遷移率。而氮氧化矽是透過氨的氮化方式與後續的氧化二氮熱處理，可以使介電常數提升至4.86，另外觀察漏電流的部分，可發現漏電流的傳導機制為Fowler-Nordheim (F-N) 穿隧機制，其導帶差為2.71 ev，綜合這些電特性，可以發現氮氧化矽薄膜具有推升鍺電晶體效率的潛力。
接著，我們發展出利用在鍺薄膜上，透過熱擴散的方式，使鍺趨入二氧化鋯內部，成為透過鍺穩定的四方晶態二氧化鋯之閘極介電層，其介電常數達到36.6，並在矽晶圓上製作鍺電容器。另外再利用熱成長的方式形成的二氧化鍺當介面層，而四方晶態二氧化鋯/二氧化鍺/鍺這樣的堆疊結構，可以使電容器有較佳的介面品質。另外再更進一步透過氫熱退火的方式，可以抑制漏電流，也使我們發展高效能結晶態的鍺電容器元件提供了一個新的方向。
除此之外，為了提升介面層的介電常數與熱穩定性，我們發展了以氧化鍺為基底的材料，以用來增強介面的品質與特性。第一種材料，透過氧化 錫/鍺與 錫鍺/鍺 結構的方式，形成氧化錫鍺薄膜，並研究在鈍化鍺金氧半元件表面的相容性。因為發現錫進入氧化鍺內部後，可以抑制氧化鍺揮發的產生。另一方面，此薄膜從電容的量測，觀察到具有很低的頻率散射現象以及很小的磁滯現象，因此可以發現具有極好的電特性。第二種材料，透過氧化釔/鍺結構的方式，形成氧化釔鍺薄膜，並研究在鈍化鍺金氧半元件表面的相容性。因為透過氧化的方式，釔原子的結合可以有效地抑制介電質與鍺之間的缺陷，減少懸浮鍵結的產生，而能有效地鈍化鍺與介面層的介面。氧化釔鍺具有少量的氧化物內部缺陷，以及達到2.1×1011 cm−2 eV−1的介面缺陷密度。除此之外，氧化釔鍺的介電常數達到10.8，比二氧化鍺的介電常數更高，且在電容量測上，也具有極低的頻率散射現象。
最後，我們發展稀土族氧化物材料為介面層，整合結晶態高介電常數材料為閘極介電層，在矽基板上製作鍺電容器。第一種堆疊結構，採用氧化釔為介面層，因為氧化釔具有較大的能隙以及有效鈍化鍺表面的效果。另外使用透過鍺穩定的四方晶態二氧化鋯來當閘極介電層，而結晶態二氧化鋯的製作方式，是利用二氧化鋯/鍺/二氧化鋯堆疊結構在經過500 oC熱退火來形成。此四方晶態二氧化鋯/氧化釔堆疊結構具有很低的磁滯，以及達到5.8×1011 cm−2 eV−1的介面缺陷密度，表現出令人滿意的電特性。第二種堆疊結構，採用氧化鐿為介面層，斜方晶態的四氧化鋯鈦來做為閘極介電層，製作出四氧化鋯鈦/氧化鐿堆疊結構之鍺電容器。因為氧化鐿具有較大的價帶差以及有效鈍化鍺表面的效果，而在600 oC退火之下，可以使非晶態四氧化鋯鈦形成斜方晶態的結晶型態，且其介電常數高達43.2。而此堆疊結構可使等效氧化層厚度降至0.76 奈米，7.8×1011 cm−2 eV−1的介面缺陷密度，以及良好的漏電流特性，以達到高效能的鍺電容器。

關鍵字

鍺 ； 高介電材料 ； 電容器 ； 電晶體 ； 氧化鋯 ； 結晶態

並列摘要

This thesis focuses on the the process fully compatible with incumbent ultra-large-scale integration (ULSI) technology, and hence, providing an economic way of fabricating high-performance Ge MOSFETs without using a Ge substrate and how to solve issues on Ge bulk device integration. We concentrate the most critical issue which obtains a high-quality interface between Ge and the high-κ dielectric. Crystalline high-κ materials were introduced to replace amorphous dielectric, since they can offer a larger physical thickness while maintaining a low EOT due to their higher κ value.
First, Metal-oxide-semiconductor (MOS) devices, using a Si substrate and a thermal SiON film as the gate dielectric on a Ge layer, have been physically and electrically characterized. The small frequency dispersion and negligible hysteresis demonstrate very few oxide traps. The efficiency of Ge surface passivation is evidenced by the acceptable interface trap density of 7.08 ×1011 cm-2 eV-1 close to midgap, which is critical for the enhancement of the carrier mobility in MOSFET devices. On the other hand, for the thermal SiON film, a higher permittivity of 4.86 can be achieved by NH3 nitridation and a subsequent N2O treatment of an as-grown SiO2 film without compromising its leakage current. The conduction mechanism is confirmed to be Fowler-Nordheim (F-N) tunneling with extracted electron barrier height of 2.71 eV. Combining with these promising properties, the SiON film shows a great potential to further boost the performance of Ge MOSFETs.
Next, a Ge-stabilized tetragonal ZrO2 (t-ZrO2) film formed by incorporating Ge atoms thermally driven from an underlying Ge layer into a ZrO2 film was investigated as the gate dielectric for Ge MOS capacitors fabricated on a Si substrate. By using a thermally-grown ultrathin GeO2 film as an interfacial layer, the t-ZrO2/GeO2/Ge stack shows improved interface characteristics and a κ value of 36.6 for the t-ZrO2. Further leakage current suppression can be achieved by a H2 annealing of the t-ZrO2/GeO2/Ge stack, which makes a paves an alternative avenue to develop a high-performance crystalline gate dielectric for Ge MOS devices.
Besides, in order to improve dielectric constant and thermal stability of interface layer, we demonstrate GeOx-based material to enhance interface quality and characteristic. The first material, SnGeOx films formed by thermal oxidation of Sn/Ge and SnGex/Ge structures were explored to investigate the capability of passivation for Ge MOS devices. It is found that Sn incorporation into germanium oxide is effective in suppressing the formation of volatile GeO. Furthermore, the films also demonstrate desirable electrical characteristics in terms of tiny frequency dispersion and small hysteresis in capacitance measurement. The second material, YGeOx formed by thermal oxidation of Y/Ge structure was to investigate the capability of passivation for Ge MOS devices. Because of the thermal oxidation nature of the process that effectively suppresses dielectric structural defects and incorporates sufficient Y atoms at the interface to well passivate the dangling bonds on Ge surface, the YGeOx enjoys a small amount of oxide traps and a low interface trap density (Dit) of 2.1×1011 cm−2 eV−1. In addition, the thermally grown YGeOx demonstrates a relatively high dielectric constant of 10.8 as compared to GeO2, tiny frequency dispersion in C-V characteristics
Finally, rare-earth oxide material is investigated as passivation layer in Ge MOS capacitors with crystalline high-κ gate dielectric. The first stack, by adopting an amorphous Y2O3 passivation layer, which provides a wide band gap and well passivates Ge surface without the presence of GeOx, a high-κ crystalline ZrO2/Y2O3 stack was explored as the gate dielectric for Ge MOS devices on Si substrate. The crystalline ZrO2 is a Ge stabilized tetragonal/cubic dielectric with the κ value of 36.1 and was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent 500 °C annealing. The high-κ crystalline ZrO2/Y2O3 gate stack shows promising electrical characteristics in terms of low Dit of 5.8×1011 cm−2 eV−1, negligible hysteresis. The second stack, by adopting an amorphous Yb2O3 passivation layer, which provides a large conduction band offset and well passivates Ge surface, a high-κ crystalline ZrTiO4/Yb2O3 stack was explored as the gate dielectric for Ge MOS devices. With 600 ◦C annealing, the ZrTiO4 film can be crystallized in orthorhombic phase and orthorhombic-ZrTiO4 enjoys an even higher κ value of 43.2. This crystalline ZrTiO4/Yb2O3 gate stack demonstrates EOT of 0.76 nm, desirable Dit of 7.8 × 1011 cm−2eV−1, and good leakage current. Therefore, the stack demonstrates good performance characteristics.

並列關鍵字

Ge ； high-k ； capacitor ； MOSFET ； ZrO2 ； crystalline

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