- 期刊
Efficient VLSI Implementation for Montgomery Multiplication in GF(2(superscript m))
並列摘要
The Montgomery multiplication algorithm without division operations is popular both in prime field GF(p) and Finite field GF(2(superscript m)). However, the Montgomery multiplication algorithm has the time-dependent problem. We will present a time-independent Montgomery multiplication algorithm. The results show that our proposed time-independent Montgomery multiplication algorithm not only saves about 50% time complexity but also saves about 11% space complexity as compared to the traditional Montgomery multiplication algorithm. Our proposed systolic array Montgomery multiplier has simplicity, regularity, modularity, and concurrency, and is very suitable for VLSI implementation.
被引用紀錄
Chang, H. W. (2013). 低複雜度及具錯誤偵測功能之有限場乘法器 [doctoral dissertation, National Taipei University of Technology]. Airiti Library. https://doi.org/10.6841/NTUT.2013.00424
Chang, C. H. (2011). 具即時錯誤偵測之有限場多項式基底乘法器設計 [doctoral dissertation, National Taipei University of Technology]. Airiti Library. https://doi.org/10.6841/NTUT.2011.00131
延伸閱讀
- MASUPE, S., & ARSLAN, T. (2000). Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors. VLSI Design, 2000(), 397-403. https://doi.org/10.1155/2000/34760
- Chen, Q. (2010). Efficient high-frequency electromagnetic simulation in VLSI [doctoral dissertation, The University of Hong Kong]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0029-1812201200017593
- Zheng, A. Y. (2020). VLSI Architecture of Non-Negative Matrix Factorization Engine for Light Field Factorization [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-0209202114072211
- Fuchs, G., & Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011(), 315-337. https://doi.org/10.1155/2011/936712
- Manikandan, R., Sindura, J., SriRavali, M., & Swaminathan, P. (2012). Efficient Mathematical Model on VLSI Circuit Partitioning. Research Journal of Applied Sciences, Engineering and Technology, 4(13), 1978-1979. https://www.airitilibrary.com/Article/Detail?DocID=20407467-201207-201510260011-201510260011-1978-1979