有限場數值計算廣泛的使用於橢圓曲線密碼與先進密碼標準等多種密碼系統中,可以加速加密或解密的處理速度。在密碼系統的有限場數值運算中,乘法運算扮演了相當重要的角色,因為複雜的有限場數值運算都可以使用乘法運算來完成,如乘法反元素運算、指數運算、和除法運算等運算。但是乘法運算相較於加法運算相對的複雜及耗時。在行動或嵌入式等資源有限的系統中,低成本的有限場數值計算硬體設計就相對重要,因此,在本文中我們提出了低成本的有限場運算架構,可以有效的降低硬體成本以及計算所需之時間。另外,近年來快速發展的植入錯誤式密碼攻擊法,是將錯誤植入加解密晶片中,再利用錯誤的輸出即可以有效的加速破解密碼系統,使得密碼系統失去應有的安全性。有鑑於此,近年來如何確保加解密資料的正確性也成為了相當重要的課題。綜合上述,本論文除了提出低成本且高速的有限場乘法的計算架構外,另外也提出了具有即時錯誤偵測能力的乘法器。
Finite field arithmetic has been widely used in many cryptosystems, particularly in the Elliptic Curve Cryptosystem (ECC) and the Advanced Encryption Standard (AES) as a method for speeding up their encryption/decryption processes. The multiplication operation is the major finite field arithmetic operation, because other complicated operations, such as multiplicative inversion, exponentiation, and division, can be performed through repeated multiplicative operations. Low-cost finite field multiplier is attractive for various mobile applications. Efficient hardware implementations of finite field multipliers in the GF(2m) are highly desirable. Therefore, this dissertation proposed low-complexity and high speed GF(2m) multiplier architecture to reduce both space and time complexities. Furthermore, recently developed fault-based cryptanalysis which faults are injected into cryptosystems has been proven to be an effective cryptanalysis method against symmetrical and asymmetrical encryption algorithms. Several error-detection approaches have been developed for finite field arithmetic architectures. In this dissertation, a polynomial basis multipliers over GF(2m) with concurrent error detection capability is also developed.