一個可應用於數位訊號處理之簡單而精確的定寬乘法器設計

定寬乘法器(fixed-width multiplier)本質上屬於近似乘法器(approximate multiplier)，可用於降低乘法運算所需之功率消耗與電路面積。因此定寬乘法器被廣泛應用於數位信號處理應用中，例如多媒體(multi-media)、數位訊號處理(digital signal processing)、類神經網路(neural network)等相關應用領域，在乘法器之輸出入資料格式本身便適用定寬乘法器。在本文中，我們提出了一種新穎的定寬乘法器設計。所提出的體系結構的主要優點是它使用簡單而準確的方法進行糾正。如同實驗結果，可以同時實現較低的功率以及較高的精確度。實驗結果顯示，此定寬乘法器設計架構確實可達到低功率及高精確度。

關鍵字

硬體電路；數位電路；邏輯電路；低功耗；近似；定寬

並列摘要

A fixed-width multiplier is essentially an approximate multiplier, which can be used to reduce power consumption and circuit area required for a multiplication operation. Fixed-width multipliers have been widely used in digital signal processing applications, such as multimedia, digital signal processing, neural network, and other related application fields, since the input/output data formats of multipliers in these application are suitable for fixed-width multipliers. In this thesis, we propose a novel fixed-width multiplier design. The main advantage of the proposed architecture is that it uses a simple yet accurate method for error correction. As a consequence, both low-power and high-accuracy can be achieved at the same time. Experimental result consistently show that proposed fixed-width multiplier architecture can achieve both low power and high accuracy.

並列關鍵字

Hardware Circuits ； Digital Circuits ； Logic Design ； Low Power ； Approximate ； Fixed-Width

參考文獻

[1] C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput., vol. EC-13, pp. 14–17, 1964.

Google Scholar

[2] C. R. Baugh and B. A.Wooley, “A two’s complement parallel array multiplication algorithm,” IEEE Trans. Comput., vol. C-22, pp. 1045–1047, Dec. 1973.