高效能低壓降線性穩壓器之分析與實作

低壓降線性穩壓器(LDO)，擁有低雜訊、體積小之特性，更因其效能之提升，近年來成爲低功率穩壓與電源管理積體電路之主流，本文針對組成一高效能LDO之架構：精準參考電電源電路、功率電晶體、誤差放大器以及回授電阻之設計加以分析、最後利用TSMC 0.35um CMOS製程技術模擬、設計完成一晶片面積約0.936×0.804平方公厘、消耗功率低於0.21mW，且輸入電壓可從1.7V至3.3V，線電壓調節率約0.43mV/V，輸出電流可從0mA至100mA，負載調節率約5mV/mA以下，輸出電壓可穩定在1.5V之高效能LDO。此外整體LDO閉迴路之頻率響應、穩定度與溫度係數等問題，也在本文中加以分析。

關鍵字

低壓降線性穩壓器；線調節率；負載調節率；誤差放大器；溫度係數

並列摘要

Low Dropout Linear Regulator (LDO) is main structure of low power management integrated circuit in recent years, due to it's low noise, high power density and improving power efficiency characteristics. In this paper, the main components within high performance LDO consist of a precision bias reference, power PMOS transistor, an error amplifier and feedback circuit are analyzed and design in detail. The proposed high performance LDO with a chip area of 0.9360.804mm^2, power dissipation of 0.21mW is designed and fabricated in a 2P4M TSMC 0.35-um CMOS process. Experimental result show that the high performance LDO functions properly with input voltage from 1.7V to 3.3V, provides an output voltage of 1.5V , with 0.43mV /V line regulation and 5mV/mA load regulation (output current from 0~100mA variation). The overall open-loop frequency response, stability of OPA and temperature coefficient are analyzed and discussed in this paper.

並列關鍵字

Low Dropout Linear Regulator ； Line Regulation ； Load Regulation ； Error Amplifier ； Temperature Coefficient

參考文獻

K. N. Leung,P. K. T. Mok,S. K. Lau(2004).A Low-Voltage CMOS Low-Dropout Regulator with Enhanced Loop Response.IEEE International Symposium on Circuits and System.(IEEE International Symposium on Circuits and System).

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