新型低功率雙邊緣觸發正反器設計

A Novel Low-Power Dual Edge-Triggered Flip-Flop Design

余建政(C. C. Yu) ； 陳冠廷(K. T. Chen)

《修平學報》 24期 (2012/03) Pp. 59-68

https://doi.org/10.29548/BGYY.201203.0005

摘要

在相同的時脈頻率下，雙邊緣觸發正反器能夠提供兩倍於單邊緣觸發正反器的資料傳輸率。在低功率VLSI電路設計中，雙邊緣觸發正反器的使用已廣泛的受到重視。本文提出一種新型低功率雙邊緣觸發正反器電路設計，並與四篇先前之雙邊緣觸發正反器電路，在不同工作電壓和不同工作頻率下，針對功率損耗和功率延遲乘積（Power-Delay Product；PDP）加以分析比較。本論文係使用TSMC 180nm的製程技術模擬。根據模擬結果顯示，本論文所提出之雙邊緣觸發正反器能有效減少功率損耗達53.8%，並能改善功率延遲乘積達70%。

關鍵字

低功率 ； 雙邊緣觸發正反器 ； 資料傳輸率

並列摘要

The dual edge-triggered flip-flops (DETFFs) use both clock edges and can provide a data rate that is twice that of single edge-triggered flip-flops for the same clock frequency. In the research of low-power VLSI circuits design, the use of DETFF has gained more attention. In this paper, we present a novel low-power DETFF design and compare four previously published DETFFs with our proposed design for their power dissipation and power-delay product (PDP), at different voltage and frequency.HSPICE simulation results employing TSMC 180nm CMOS technology indicate the proposed flip-flop can reduce effectively power dissipation up to 53.8% as compared to other DETFFs. Moreover, the improvement in power-delay product is enhanced up to 70%.

並列關鍵字

low-power ； dual edge-triggered flip-flop ； data rate

參考文獻

J. Tschanz, S. Narendra, Z. Chen, S. Borkar, and M. Sachdev, “Comparative Delay and Energy of Single Edge-Triggered & Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors, ” in Symp. VLSI Circuits Dig. Tech. Papers, 2001, pp. 217-218.

S. H. Unger, “Double Edge-Triggered Flip-Flops,” IEEE Trans. Comput., vol. C-30, no. 6, pp. 1652-1655, June 1981.

A. Gago, R. Escano, and J. A. Hidalgo, “Reduced Implementation of D-type DET Flip-Flops,” IEEE J. Solid-State Circuits, vol. 28, pp. 400-442, Mar. 1993.

R. Hossain, L. D. Wronski, and A. Albicki, “Low Power Design Using Double Edge Triggered Flip-Flops,” IEEE Trans. VLSI Syst., vol.2, no. 2, pp.261-265, June 1994.

R. P. Llopis and M. Sachdev, “Low Power, Testable Dual Edge Triggered Flip-Flops,” in 1996 Int. Symp. Low Power Electronics and Design, 1996, pp. 341-345.